Datasheet > CY2SSTU32864BFXCT

CY2SSTU32864BFXCT

更新时间： 2024-10-01 03:12:59

品牌	Logo	应用领域
SPECTRALINEAR		触发器逻辑集成电路
页数	文件大小	规格书
9页	98K
描述
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register

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CY2SSTU32864

1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register

The device monitors both DCS# and CSR# inputs and will gate

the Qn outputs from changing states when both DCS# and

Features

• Operating frequency: DC to 500 MHz

• Supports DDRII SDRAM

CSR# inputs are high. If either DCS# or CSR# input is low, the

Qn outputs will function normally. The RESET input has priority

over the DCS# and CSR# control and will force the outputs

low. If the DCS#-control functionality is not desired, the CSR#

input can be hardwired to ground, in which case the set-up

time requirement for DCS# would be the same as for the other

D data inputs.

• Two operations modes: 25 bit (1:1) and 14 bit (1:2)

• 1.8V operation

• Fully JEDEC-compliant (JESD82-7A)

• 96-ball FBGA

The device supports low-power standby operation. When the

reset input (RESET#) is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference

voltage (VREF) inputs are allowed. In addition, when RESET#

is low, all registers are reset and all outputs are forced low. The

LVCMOS RESET# and Cn inputs must always be held at a

valid logic high or low level. To ensure defined outputs from the

must be held in the low state during power-up.

Functional Description

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8V CMOS drivers that have been optimized to

drive the DDR-II DIMM load. The CY2SSTU32864 operates

from a differential clock (CK and CK#). Data are registered at

the crossing of CK going high, and CK# going low.

In the DDR-II RDIMM application, RESET# is specified to be

completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven low quickly, relative to the time to

disable the differential input receivers. However, when coming

out of reset, the register will become active quickly, relative to

the time to enable the differential input receivers.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when low) to B configuration (when

high). The C1 input controls the pinout configuration from

25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and

C1 = 0 is not allowed and it will default to the C0 = C1 = 0 state.

Pin Configurations

DCKE NC

VREF VDD QCKEA QCKEB

DCKE NC

VREF VDD QCKE NC

VREF VDD Q1A

GND GND Q2A

VDD VDD Q3A

GND GND Q4A

VDD VDD Q5A

GND GND Q6A

Q1B

GND GND Q2A

VDD VDD Q3A

Q2B

Q3B

Q2B

Q3B

Q4B

Q5B

Q6B

D15

D16

GND GND Q2

VDD VDD Q3

Q15

Q16

DODT NC

GND GND QODTA QODTB

DODT NC

GND GND QODT NC

VDD VDD Q5A

GND GND Q6A

Q5B

Q6B

D17

D18

VDD VDD Q5

GND GND Q6

Q17

Q18

RST# VDD VDD C1

DCS# GND GND QCSA# QCSB#

CSR# VDD VDD ZOH ZOL

DCS# GND GND QCSA# QCSB#

CSR# VDD VDD ZOH ZOL

DCS# GND GND QCS# NC

CSR# VDD VDD ZOH ZOL

CK#

GND GND Q8A

VDD VDD Q9A

Q8B

Q9B

GND GND Q8A

VDD VDD Q9A

Q8B

Q9B

D19

D20

D21

D22

D23

D24

D25

GND GND Q8

VDD VDD Q9

GND GND Q10

VDD VDD Q11

GND GND Q12

VDD VDD Q13

VREF VDD Q14

Q19

Q20

Q21

Q22

Q23

Q24

Q25

D10

D11

D12

D13

D14

GND GND Q10A Q10B

VDD VDD Q11A Q11B

GND GND Q12A Q12B

VDD VDD Q13A Q13B

VREF VDD Q14A Q14B

D10

GND GND Q10A Q10B

VDD VDD QODTA QODTB

D10

D11

D12

D13

D14

DODT NC

D12

D13

GND GND Q12A Q12B

VDD VDD Q13A Q13B

VREF VDD QCKEA QCKEB

DCKE NC

1:2 Register A C0 = 0, C1 = 1

1:2 Register B C0 = 1, C1 = 1

1:1 Register C0 = 0, C1 = 0

Rev 1.0, November 25, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 9

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7...9

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与CY2SSTU32864BFXCT相关器件

型号	品牌	获取价格	描述	数据表
CY2SSTU32866	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
CY2SSTU32866BFXC	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
CY2SSTU32866BFXCT	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
CY2SSTU877	SPECTRALINEAR	获取价格	1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877_06	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVC-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVC-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVI-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVI-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

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