Datasheet > CY2SSTU877BVXI-43T

CY2SSTU877BVXI-43T

更新时间： 2024-11-24 03:18:31

品牌	Logo	应用领域
SPECTRALINEAR		逻辑集成电路驱动
页数	文件大小	规格书
8页	136K
描述
1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer

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CY2SSTU877

1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

distributes a differential clock input pair (CK, CK#) to ten differ-

ential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential

pair of feedback clock outputs (FBOUT, FBOUT#).

Features

• Operating frequency: 125 MHz to 500 MHz

• Supports DDRII SDRAM

The input clocks (CK, CK#), the feedback clocks (FBIN,

FBIN#), the LVCMOS (OE, OS), and the analog power input

(AVDD) control the clock outputs.

• 1 to 10 differential clock buffer (SSTL_18)

• Spread-Spectrum-compatible

• Low jitter (cycle-to-cycle): 40 ps

• Very low output-to-output skew: 40 ps

• Auto power-down feature when input is low

• 1.8V operation

The PLL in the CY2SSTU877 clock driver uses the input

clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to

provide high-performance, low-skew, low-jitter output differ-

ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able

to track Spread Spectrum Clocking (SSC) for reduced EMI.

When AVDD is grounded, the PLL is turned off and bypassed

for test purposes. When both clock signals (CK, CK#) are logic

low, the device will enter a low-power mode. An input logic

detection circuit on the differential inputs, independent from

the input buffers, will detect the logic low level and perform a

low-power state where all outputs, the feedback, and the PLL

are OFF. When the inputs transition from both being logic low

to being differential signals, the PLL will be turned back on, the

inputs and outputs will be enabled and the PLL will obtain

phase lock between the feedback clock pair (FBIN, FBIN#)

and the input clock pair (CK, CK#) within the specified stabili-

zation time t_L.

• Fully JEDEC-compliant (JESD 82-8)

• 52-ball BGA

Functional Description

The CY2SSTU877 is a high-performance, low-skew, low-jitter

zero delay buffer designed to distribute differential clocks in

high-speed applications.

This phase-locked loop (PLL) clock buffer is designed for a

V_DDof 1.8V, an AV_DDof 1.8V and SSTL18 differential data

input and output levels. This device is a zero delay buffer that

Pin Configuration

Block Diagram

CLKT1

CLKC1

CLKC2

CLKT2

CLKT0

GND

CLKC0 CLKC5 CLKT5

CLKT6

CLKC6

CLKC7

CLKT7

FB_INT

FB_INC

GND

VDDQ

CLK_INT VDDQ

CLK_INC VDDQ

VDDQ

AGND

AVDD

CLKT3

VDDQ

GND

VDDQ

VDDQ FB_OUTC

GND FB_OUTT

GND

CLKT9

GND

CLKT8

CLKC3 CLKC4 CLKT4

CLKC9 CLKC8

52 BGA

Rev 1.0, November 21, 2006

Page 1 of 8

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7 8

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与CY2SSTU877BVXI-43T相关器件

型号	品牌	获取价格	描述	数据表
CY2SSTU877BVXI-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVXI-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFC-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFC-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFI-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFI-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFXC-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFXC-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFXI-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877LFXI-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

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