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CY2SSTU32866BFXC PDF预览

CY2SSTU32866BFXC

更新时间: 2024-11-20 03:12:59
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SPECTRALINEAR /
页数 文件大小 规格书
24页 236K
描述
1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity

CY2SSTU32866BFXC 数据手册

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CY2SSTU32866  
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant  
Data Register with Parity  
CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,  
the Qn outputs will function normally. The RESET# input has  
Features  
• Operating frequency: DC to 500 MHz  
• Supports DDRII SDRAM  
priority over the DCS# and CSR# control and will force the  
outputs LOW. If the DCS#-control functionality is not desired,  
the CSR# input can be hardwired to ground, in which case the  
set-up time requirement for DCS# would be the same as for  
the other D data inputs.  
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)  
• 1.8V operation  
The device supports low-power standby operation. When the  
reset input (RESET#) is LOW, the differential input receivers  
are disabled, and undriven (floating) data, clock, and reference  
voltage (VREF) inputs are allowed. In addition, when RESET#  
is LOW, all registers are reset and all outputs are forced LOW.  
The LVCMOS RESET# and Cn inputs must always be held at  
a valid logic HIGH or LOW level. To ensure defined outputs  
from the register before a stable clock has been supplied,  
RESET# must be held in the LOW state during power-up.  
• Fully JEDEC-compliant (JESD 82-10)  
• 96-ball FBGA  
Functional Description  
All clock and data inputs are compatible with the JEDEC  
standard for SSTL_18. The control inputs are LVCMOS. All  
outputs are 1.8-V CMOS drivers that have been optimized to  
drive the DDR-II DIMM load. The CY2SSTU32866 operates  
from a differential clock (CK and CK#). Data are registered at  
the crossing of CK going high, and CK# going LOW.  
In the DDR-II RDIMM application, RESET# is specified to be  
completely asynchronous with respect to CK and CK#.  
Therefore, no timing relationship can be guaranteed between  
the two. When entering reset, the register will be cleared and  
the outputs will be driven low quickly, relative to the time to  
disable the differential input receivers. However, when coming  
out of reset, the register will become active quickly, relative to  
the time to enable the differential input receivers.  
The C0 input controls the pinout configuration of the 1:2 pinout  
from A configuration (when LOW) to B configuration (when  
HIGH). The C1 input controls the pinout configuration from  
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).  
The device monitors both DCS# and CSR# inputs and will gate  
the Qn outputs from changing states when both DCS# and  
Pin Configuration  
1
2
DCKE PPO  
3
VREF VDD  
4
5
QCKE NC  
6
1
2
PPO  
NC  
3
4
5
6
1
DCKE PPO  
2
3
4
5
6
A
B
C
D
E
F
A
B
C
D
E
F
D1  
D2  
D3  
D4  
D5  
D6  
VREF VDD  
GND GND Q2A  
VDD VDD Q3A  
Q1A  
Q1B  
A
B
C
D
E
F
VREF VDD  
GND GND Q2A  
VDD VDD Q3A  
QCKEA QCKEB  
Q2B  
Q3B  
Q4B  
Q5B  
Q6B  
C0  
D2  
D3  
D15  
D16  
GND GND Q2  
Q3  
Q15  
Q16  
D2  
D3  
NC  
NC  
Q2B  
Q3B  
NC  
VDD  
VDD  
QERR# GND GND Q4A  
DODT QERR# GND GND QODT NC  
DODT QERR# GND GND QODTA QODTB  
NC  
NC  
VDD  
GND GND Q6A  
VDD C1  
VDD  
Q5A  
D5  
D6  
D17  
D18  
VDD  
GND GND Q6  
VDD C1  
VDD  
Q5  
Q17  
Q18  
C0  
D5  
D6  
NC  
NC  
VDD  
GND GND Q6A  
VDD C1  
VDD  
Q5A  
Q5B  
Q6B  
C0  
G
H
J
PAR_IN RST# VDD  
G
H
J
PAR_IN RST# VDD  
G
H
J
PAR_IN RST# VDD  
CK  
CK#  
D8  
DCS# GND GND QCSA# QCSB#  
CK  
DCS# GND GND QCS# NC  
CK  
DCS# GND GND QCSA# QCSB#  
CSR# VDD  
VDD  
GND GND Q8A  
VDD VDD Q9A  
ZOH  
ZOL  
Q8B  
Q9B  
CK#  
D8  
CSR# VDD  
VDD  
GND GND Q8  
VDD VDD Q9  
GND GND Q10  
VDD VDD Q11  
GND GND Q12  
ZOH  
ZOL  
Q19  
Q20  
Q21  
Q22  
Q23  
Q24  
Q25  
CK#  
D8  
CSR# VDD  
VDD  
GND GND Q8A  
VDD VDD Q9A  
ZOH  
ZOL  
Q8B  
Q9B  
K
L
NC  
NC  
NC  
K
L
D19  
D20  
D21  
D22  
D23  
D24  
D25  
K
L
NC  
NC  
NC  
NC  
NC  
NC  
NC  
D9  
D10  
D9  
D9  
M
N
P
R
T
GND GND Q10A Q10B  
VDD VDD QODTA QODTB  
GND GND Q12A Q12B  
M
N
P
R
T
D10  
D11  
D12  
D13  
D14  
M
N
P
R
T
D10  
D11  
D12  
D13  
D14  
GND GND Q10A Q10B  
VDD VDD Q11A Q11B  
GND GND Q12A Q12B  
DODT NC  
D12  
D13  
NC  
NC  
VDD VDD  
VREF VDD  
Q13A Q13B  
QCKEA QCKEB  
VDD VDD  
VREF VDD  
Q13  
Q14  
VDD VDD  
VREF VDD  
Q13A Q13B  
Q14A Q14B  
DCKE NC  
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
1:2 Register A C0 = 0, C1=1  
1:2 Register B C0 = 1, C1=1  
1:1 Register C0 = 0, C1=0  
Rev 1.0, November 25, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 24  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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