Datasheet > CY2SSTU32866

CY2SSTU32866

更新时间： 2024-11-20 03:12:59

品牌	Logo	应用领域
SPECTRALINEAR		/
页数	文件大小	规格书
24页	236K
描述
1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY2SSTU32866 数据手册

CY2SSTU32866

1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant

Data Register with Parity

CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,

the Qn outputs will function normally. The RESET# input has

Features

• Operating frequency: DC to 500 MHz

• Supports DDRII SDRAM

priority over the DCS# and CSR# control and will force the

outputs LOW. If the DCS#-control functionality is not desired,

the CSR# input can be hardwired to ground, in which case the

set-up time requirement for DCS# would be the same as for

the other D data inputs.

• Two operations modes: 25 bit (1:1) and 14 bit (1:2)

• 1.8V operation

The device supports low-power standby operation. When the

reset input (RESET#) is LOW, the differential input receivers

are disabled, and undriven (floating) data, clock, and reference

voltage (VREF) inputs are allowed. In addition, when RESET#

is LOW, all registers are reset and all outputs are forced LOW.

The LVCMOS RESET# and Cn inputs must always be held at

a valid logic HIGH or LOW level. To ensure defined outputs

from the register before a stable clock has been supplied,

RESET# must be held in the LOW state during power-up.

• Fully JEDEC-compliant (JESD 82-10)

• 96-ball FBGA

Functional Description

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized to

drive the DDR-II DIMM load. The CY2SSTU32866 operates

from a differential clock (CK and CK#). Data are registered at

the crossing of CK going high, and CK# going LOW.

In the DDR-II RDIMM application, RESET# is specified to be

completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven low quickly, relative to the time to

disable the differential input receivers. However, when coming

out of reset, the register will become active quickly, relative to

the time to enable the differential input receivers.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when LOW) to B configuration (when

HIGH). The C1 input controls the pinout configuration from

25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).

The device monitors both DCS# and CSR# inputs and will gate

the Qn outputs from changing states when both DCS# and

Pin Configuration

DCKE PPO

VREF VDD

QCKE NC

PPO

DCKE PPO

VREF VDD

GND GND Q2A

VDD VDD Q3A

Q1A

Q1B

VREF VDD

GND GND Q2A

VDD VDD Q3A

QCKEA QCKEB

Q2B

Q3B

Q4B

Q5B

Q6B

D15

D16

GND GND Q2

Q15

Q16

Q2B

Q3B

VDD

QERR# GND GND Q4A

DODT QERR# GND GND QODT NC

DODT QERR# GND GND QODTA QODTB

VDD

GND GND Q6A

VDD C1

VDD

Q5A

D17

D18

VDD

GND GND Q6

VDD C1

VDD

Q17

Q18

VDD

GND GND Q6A

VDD C1

VDD

Q5A

Q5B

Q6B

PAR_IN RST# VDD

CK#

DCS# GND GND QCSA# QCSB#

DCS# GND GND QCS# NC

DCS# GND GND QCSA# QCSB#

CSR# VDD

VDD

GND GND Q8A

VDD VDD Q9A

ZOH

ZOL

Q8B

Q9B

CK#

CSR# VDD

VDD

GND GND Q8

VDD VDD Q9

GND GND Q10

VDD VDD Q11

GND GND Q12

ZOH

ZOL

Q19

Q20

Q21

Q22

Q23

Q24

Q25

CK#

CSR# VDD

VDD

GND GND Q8A

VDD VDD Q9A

ZOH

ZOL

Q8B

Q9B

D19

D20

D21

D22

D23

D24

D25

D10

GND GND Q10A Q10B

VDD VDD QODTA QODTB

GND GND Q12A Q12B

D10

D11

D12

D13

D14

D10

D11

D12

D13

D14

GND GND Q10A Q10B

VDD VDD Q11A Q11B

GND GND Q12A Q12B

DODT NC

D12

D13

VDD VDD

VREF VDD

Q13A Q13B

QCKEA QCKEB

VDD VDD

VREF VDD

Q13

Q14

VDD VDD

VREF VDD

Q13A Q13B

Q14A Q14B

DCKE NC

1:2 Register A C0 = 0, C1=1

1:2 Register B C0 = 1, C1=1

1:1 Register C0 = 0, C1=0

Rev 1.0, November 25, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 24

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

12 3 4 5 6 7...24

中文翻译

下载PDF

与CY2SSTU32866相关器件

型号	品牌	获取价格	描述	数据表
CY2SSTU32866BFXC	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
CY2SSTU32866BFXCT	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
CY2SSTU877	SPECTRALINEAR	获取价格	1.8V, 500MHz 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877_06	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVC-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVC-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVI-XX	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVI-XXT	CYPRESS	获取价格	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
CY2SSTU877BVXC	CYPRESS	获取价格	PLL Based Clock Driver, SSTU Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, 4.5

与CY2SSTU32866相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

25
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

17
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

49
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2SSTU32866

CY2SSTU32866 数据手册

与CY2SSTU32866相关器件

与CY2SSTU32866相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2SSTU32866

CY2SSTU32866 数据手册

与CY2SSTU32866相关器件

与CY2SSTU32866相关文章

您还可以找

您在本页遇到什么问题？