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CY2PP3220AI

更新时间： 2024-10-01 03:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
9页 191K
描述
Dual 1:10 Differential Clock / Data Fanout Buffer

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中文翻译

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CY2PP3220AI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP52,.47SQ针数：52
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.88其他特性：ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V; ALSO OPERATES AT 3.3V SUPPLY
系列：2PP输入调节：DIFFERENTIAL
JESD-30 代码：S-PQFP-G52JESD-609代码：e0
长度：10 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
最大I（ol）：0.005 A功能数量：2
反相输出次数：端子数量：52
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP52,.47SQ
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：240电源：+-2.5/+-3.3 V
Prop。Delay @ Nom-Sup：0.75 ns传播延迟（tpd）：0.75 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

CY2PP3220AI 数据手册

 浏览型号CY2PP3220AI的Datasheet PDF文件第2页浏览型号CY2PP3220AI的Datasheet PDF文件第3页浏览型号CY2PP3220AI的Datasheet PDF文件第4页浏览型号CY2PP3220AI的Datasheet PDF文件第5页浏览型号CY2PP3220AI的Datasheet PDF文件第6页浏览型号CY2PP3220AI的Datasheet PDF文件第7页 
FastEdge™ Series  
CY2PP3220  
Dual 1:10 Differential Clock/Data Fanout Buffer  
Features  
Functional Description  
The CY2PP3220 is a low-skew, low propagation delay dual  
• Two sets of ten ECL/PECL differential outputs  
• Two ECL/PECL differential inputs  
• Hot-swappable/-insertable  
• 50 ps output-to-output skew  
• 150 ps device-to-device skew  
1-to-10 differential fanout buffer targeted to meet the require-  
ments of high-performance clock and data distribution applica-  
tions. The device is implemented on SiGe technology and has  
a fully differential internal architecture that is optimized to  
achieve low signal skews at operating frequencies of up to 1.5  
GHz.  
The device features two differential input paths that are differ-  
ential internally. The CY2PP3220 may function not only as a  
differential clock buffer but also as a signal-level translator and  
fanout on ECL/PECL signal to twenty ECL/PECL differential  
loads. An external bias pin, VBB, is provided for this purpose.  
In such an application, the VBB pin should be connected to  
either one of the CLKA# or CLKB# inputs and bypassed to  
ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used  
to provide the reference level to a receiving single-ended input  
that might have a different self-bias point.  
Since the CY2PP3220 introduces negligible jitter to the timing  
budget, it is the ideal choice for distributing high frequency,  
high precision clocks across back-planes and boards in com-  
munication systems. Furthermore, advanced circuit design  
schemes, such as internal temperature compensation, ensure  
that the CY2PP3220 delivers consistent performance over  
various platforms.  
• 500 ps propagation delay (typical)  
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)  
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%  
with VEE = 0V  
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%  
with VCC = 0V  
• Industrial temperature range: –40°C to 85°C  
• 52-pin 1.4-mm TQFP package  
• Temperature compensation like 100K ECL  
• Pin compatible with MC100ES6220  
Pin Configuration  
Block Diagram  
QA0  
VCC  
QA0#  
49  
52 51  
1
2
3
48  
45 44 43  
47 46  
50  
42 41 40  
39  
QA6  
QA6#  
QA7  
QA7#  
QA8  
QA8#  
QA9  
QA9#  
VCC  
VCC  
VEE  
CLKA  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
CLKA#  
CLKA  
CLKA#  
VBB  
CLKB  
CLKB#  
VEE  
4
5
6
7
8
9
VEE  
QA9  
QA9#  
QB0  
CY2PP3220  
VCC  
QB0#  
QB0  
QB0#  
QB1  
QB1#  
VCC  
VEE  
QB9#  
QB9  
QB8#  
QB8  
CLKB  
10  
11  
12  
13  
14 15  
CLKB#  
VEE  
VEE  
QB9  
27  
QB9#  
VBB  
17  
18  
21 22 23  
19 20  
16  
24 25 26  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07513 Rev.*C  
Revised July 28, 2004  
1234567...9

中文翻译

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