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CY2PP3210AIT PDF预览

CY2PP3210AIT

更新时间： 2024-10-01 03:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路
页数 文件大小 规格书
9页 275K
描述
Dual 1:5 Differential Clock / Data Fanout Buffer

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中文翻译

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CY2PP3210AIT 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-32针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.88Is Samacsys：N
其他特性：ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V; ALSO OPERATES AT 3.3V SUPPLY系列：2PP
输入调节：DIFFERENTIALJESD-30 代码：S-PQFP-G32
JESD-609代码：e0长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大I（ol）：0.005 A
功能数量：2反相输出次数：
端子数量：32实输出次数：5
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：240
电源：+-2.5/+-3.3 VProp。Delay @ Nom-Sup：0.75 ns
传播延迟（tpd）：0.75 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
Base Number Matches：1

CY2PP3210AIT 数据手册

 浏览型号CY2PP3210AIT的Datasheet PDF文件第2页浏览型号CY2PP3210AIT的Datasheet PDF文件第3页浏览型号CY2PP3210AIT的Datasheet PDF文件第4页浏览型号CY2PP3210AIT的Datasheet PDF文件第5页浏览型号CY2PP3210AIT的Datasheet PDF文件第6页浏览型号CY2PP3210AIT的Datasheet PDF文件第7页 
FastEdge™ Series  
CY2PP3210  
Dual 1:5 Differential Clock/Data Fanout Buffer  
Features  
Functional Description  
The CY2PP3210 is a low-skew, low propagation delay dual  
• Dual sets of five ECL/PECL differential outputs  
• Two ECL/PECL differential inputs  
• Hot-swappable/-insertable  
• 50 ps output-to-output skew  
• 150 ps device-to-device skew  
1-to-5 differential fanout buffer targeted to meet the require-  
ments of high-performance clock and data distribution applica-  
tions. The device is implemented on SiGe technology and has  
a fully differential internal architecture that is optimized to  
achieve low signal skews at operating frequencies of up to 1.5  
GHz.  
The device features two differential input paths that are differ-  
ential internally. The CY2PP3210 may function not only as a  
differential clock buffer but also as a signal-level translator and  
fanout distributing a single-ended signal. An external bias pin,  
VBB, is provided for this purpose. In such an application, the  
VBB pin should be connected to either one of the CLKA# or  
CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.  
Traditionally, in ECL, it is used to provide the reference level  
to a receiving single-ended input that might have a differential  
bias point.  
Since the CY2PP3210 introduces negligible jitter to the timing  
budget, it is the ideal choice for distributing high frequency,  
high precision clocks across back-planes and boards in  
communication systems. Furthermore, advanced circuit  
design schemes, such as internal temperature compensation,  
ensure that the CY2PP3210 delivers consistent performance  
over various platforms.  
• 500 ps propagation delay (typical)  
• 0.8 ps RMS period jitter (max.)  
• 1.5 GHz Operation (2.2 GHz max. toggle frequency)  
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%  
with VEE = 0V  
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%  
with VCC = 0V  
• Industrial temperature range: –40°C to 85°C  
• 32-pin 1.4-mm TQFP package  
• Temperature compensation like 100K ECL  
• Pin compatible with MC100ES6210  
Block Diagram  
Pin Configuration  
QA0  
QA0#  
QA1  
QA1#  
VCC  
CLKA  
QA2  
QA2#  
CLKA#  
VEE  
QA3  
1
2
3
4
5
6
7
8
VCC  
NC  
CLKA  
CLKA#  
VBB  
CLKB  
CLKB#  
VEE  
QA3  
QA3#  
QA4  
QA4#  
QB0  
QB0#  
QB1  
QB1#  
24  
23  
22  
21  
20  
19  
18  
17  
QA3#  
QA4  
QA4#  
CY2PP3210  
QB0  
QB0#  
QB1  
VCC  
QB1#  
CLKB  
QB2  
QB2#  
CLKB#  
VEE  
QB3  
QB3#  
QB4  
QB4#  
VBB  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07508 Rev.*C  
Revised July 28, 2004  
1234567...9

中文翻译

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