Datasheet > CY2PP318JIT

CY2PP318JIT

更新时间： 2024-11-20 21:14:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动逻辑集成电路
页数	文件大小	规格书
8页	162K
描述
Low Skew Clock Driver, 2PP Series, 8 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC, LCC-28

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技术参数
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CY2PP318JIT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V; ALSO OPERATES AT 3.3V SUPPLY
系列：	2PP	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e0
长度：	11.5316 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	28	实输出次数：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225	传播延迟（tpd）：	0.68 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.05 ns
座面最大高度：	4.572 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	11.5316 mm
最小 fmax：	1500 MHz	Base Number Matches：	1

CY2PP318JIT 数据手册

FastEdge™ Series

CY2PP318

1of2:8DifferentialClock/DataFanoutBuffer

Features

Functional Description

The CY2PP318 is a low-skew, low propagation delay 1-to-8

differential fanout buffer targeted to meet the requirements of

high-performance clock and data distribution applications. The

device is implemented on SiGe technology and has a fully

differential internal architecture that is optimized to achieve

low signal skews at operating frequencies of up to 1.5 GHz.

• Eight ECL/PECL differential outputs

• Two ECL/PECL differential inputs

• Hot-swappable/-insertable

• 50 ps output-to-output skew

• 150 ps device-to-device skew

• 500 ps propagation delay (typical)

• 1.5 GHz Operation (2.2 GHz max. toggle frequency)

• 1.2 ps RMS period jitter (typ.)

• PECL mode supply range: V_CC= 2.5V± 5% to 3.3V±5%

with V_EE= 0V

The device features two differential input paths that are multi-

plexed internally. This mux is controlled by the CLK_SEL pin.

The CY2PP318 may function not only as a differential clock

buffer but also as a signal-level translator and fanout on

ECL/PECL signal to eight ECL/PECL differential loads. An ex-

ternal bias pin, VBB, is provided for this purpose. In such an

application, the VBB pin should be connected to either one of

the CLKA# or CLKB# inputs and bypassed to ground via a

0.01-µF capacitor.

• ECL mode supply range: V_{E E}= –2.5V± 5% to –3.3V±5%

with V_CC= 0V

• Industrial temperature range: –40°C to 85°C

• 28-pin PLCC package

Since the CY2PP318 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in

communication systems. Furthermore, advanced circuit

design schemes, such as internal temperature compensation,

ensure that the CY2PP318 delivers consistent performance

over various platforms.

• Temperature compensation like 100K ECL

Pin Configuration

Block Diagram

Q0#

Q1#

VCC

Q2#

CLKA

Q 0

C L K B #

N C

CLKA#

Q 0 #

Q 1

Q 7 #

Q3#

C Y 2 P P 3 1 8

V C C

VEE

VCC

V C C

T O P V IE W

Q 1 #

Q 7

Q 6 #

Q 6

Q 2

Q4#

CLKB

Q 2 #

CLKB#

Q5#

VEE

CLK_SEL

Q6#

VEE

Q7#

VBB

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07501 Rev.*E

Revised July 27, 2004

12 3 4 5 6 7 8

中文翻译

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与CY2PP318JIT相关器件

型号	品牌	获取价格	描述	数据表
CY2PP3210	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3210AI	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3210AIT	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3220	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AI	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AIT	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP326	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AI	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AIT	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2SSTU32864	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register

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