CY2PP3210AI

更新时间： 2024-10-01 03:12:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	275K
描述
Dual 1:5 Differential Clock / Data Fanout Buffer

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CY2PP3210AI 数据手册

FastEdge™ Series

CY2PP3210

Dual 1:5 Differential Clock/Data Fanout Buffer

Features

Functional Description

The CY2PP3210 is a low-skew, low propagation delay dual

• Dual sets of five ECL/PECL differential outputs

• Two ECL/PECL differential inputs

• Hot-swappable/-insertable

• 50 ps output-to-output skew

• 150 ps device-to-device skew

1-to-5 differential fanout buffer targeted to meet the require-

ments of high-performance clock and data distribution applica-

tions. The device is implemented on SiGe technology and has

a fully differential internal architecture that is optimized to

achieve low signal skews at operating frequencies of up to 1.5

GHz.

The device features two differential input paths that are differ-

ential internally. The CY2PP3210 may function not only as a

differential clock buffer but also as a signal-level translator and

fanout distributing a single-ended signal. An external bias pin,

VBB, is provided for this purpose. In such an application, the

VBB pin should be connected to either one of the CLKA# or

CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.

Traditionally, in ECL, it is used to provide the reference level

to a receiving single-ended input that might have a differential

bias point.

Since the CY2PP3210 introduces negligible jitter to the timing

budget, it is the ideal choice for distributing high frequency,

high precision clocks across back-planes and boards in

communication systems. Furthermore, advanced circuit

design schemes, such as internal temperature compensation,

ensure that the CY2PP3210 delivers consistent performance

over various platforms.

• 500 ps propagation delay (typical)

• 0.8 ps RMS period jitter (max.)

• 1.5 GHz Operation (2.2 GHz max. toggle frequency)

• PECL mode supply range: V_CC= 2.5V± 5% to 3.3V±5%

with V_EE= 0V

• ECL mode supply range: V_{E E}= –2.5V± 5% to –3.3V±5%

with V_CC= 0V

• Industrial temperature range: –40°C to 85°C

• 32-pin 1.4-mm TQFP package

• Temperature compensation like 100K ECL

• Pin compatible with MC100ES6210

Block Diagram

Pin Configuration

QA0

QA0#

QA1

QA1#

V_CC

CLKA

QA2

QA2#

CLKA#

V_EE

QA3

VCC

CLKA

CLKA#

VBB

CLKB

CLKB#

VEE

QA3

QA3#

QA4

QA4#

QB0

QB0#

QB1

QB1#

QA3#

QA4

QA4#

CY2PP3210

QB0

QB0#

QB1

V_CC

QB1#

CLKB

QB2

QB2#

CLKB#

V_EE

QB3

QB3#

QB4

QB4#

VBB

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07508 Rev.*C

Revised July 28, 2004

12 3 4 5 6 7...9

中文翻译

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CY2PP3210AI 替代型号

型号	品牌	替代类型	描述	数据表
MC100LVEP210FAG	ONSEMI	功能相似	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP210FARG	ONSEMI	功能相似	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver

与CY2PP3210AI相关器件

型号	品牌	获取价格	描述	数据表
CY2PP3210AIT	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer
CY2PP3220	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AI	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP3220AIT	CYPRESS	获取价格	Dual 1:10 Differential Clock / Data Fanout Buffer
CY2PP326	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AI	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2PP326AIT	CYPRESS	获取价格	2 x 2 Clock and Data Switch Buffer
CY2SSTU32864	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
CY2SSTU32864BFXC	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
CY2SSTU32864BFXCT	SPECTRALINEAR	获取价格	1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register

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