MC100LVEP210FAG

更新时间： 2024-09-23 05:27:19

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
9页	159K
描述
2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver

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MC100LVEP210FAG 数据手册

MC100LVEP210

2.5V / 3.3Vꢀ1:5 Dual

Differential ECL/PECL/HSTL

Clock Driver

Description

http://onsemi.com

MARKING

The MC100LVEP210 is a low skew 1−to−5 dual differential driver,

designed with clock distribution in mind. The ECL/PECL input

signals can be either differential or single−ended if the V output is

DIAGRAM*

used. The signal is fanned out to 5 identical differential outputs. HSTL

inputs can be used when the EP210 is operating in PECL mode.

The LVEP210 specifically guarantees low output−to−output skew.

Optimal design, layout, and processing minimize skew within a device

and from device to device.

To ensure the tight skew specification is realized, both sides of the

differential output need to be terminated identically into 50 W even if

only one output is being used. If an output pair is unused, both outputs

may be left open (unterminated) without affecting skew.

MC100

LVEP21

AWLYYWWG

32−LEAD LQFP

FA SUFFIX

CASE 873A

The MC100LVEP210, as with most other ECL devices, can be

operated from a positive V supply in PECL mode. This allows the

LVEP210 to be used for high performance clock distribution in +3.3 V

or +2.5 V systems. Single−ended CLK input operation is limited to a

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

≥ 3.0 V in PECL mode, or V ≤ −3.0 V in ECL mode.

Designers can take advantage of the LVEP210’s performance to

distribute low skew clocks across the backplane or the board. In a

PECL environment, series or Thevenin line terminations are typically

used as they require no additional power supplies. For more

information on using PECL, designers should refer to Application

Note AN1406/D.

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Features

• 85 ps Typical Device−to−Device Skew

• 20 ps Typical Output−to−Output Skew

• V Output

• Jitter Less than 1 ps RMS

• 350 ps Typical Propagation Delay

• Maximum Frequency u 3 GHz Typical

• The 100 Series Contains Temperature Compensation

• PECL and HSTL Mode Operating Range: V = 2.375 V to 3.8 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −2.375 V to −3.8 V

• Open Input Default State

• LVDS Input Compatible

• Fully Compatible with MC100EP210

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

June, 2006 − Rev. 12

MC100LVEP210/D

12 3 4 5 6 7...9

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MC100LVEP210FAG 替代型号

型号	品牌	替代类型	描述	数据表
MC100LVEP210FARG	ONSEMI	完全替代	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP210FAR2	ONSEMI	类似代替	Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver
MC100LVEP210FA	ONSEMI	功能相似	Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

与MC100LVEP210FAG相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEP210FAR2	ONSEMI	获取价格	Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver
MC100LVEP210FARG	ONSEMI	获取价格	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP210MNG	ONSEMI	获取价格	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP210MNR2G	ONSEMI	获取价格	2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
MC100LVEP34	ONSEMI	获取价格	2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip
MC100LVEP34_06	ONSEMI	获取价格	2.5V / 3.3V ECL ±2, ±4, ±8 Clock Generation C
MC100LVEP34D	ONSEMI	获取价格	2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip
MC100LVEP34DG	ONSEMI	获取价格	2.5V / 3.3V ECL ±2, ±4, ±8 Clock Generation C
MC100LVEP34DR2	ONSEMI	获取价格	2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip
MC100LVEP34DR2G	ONSEMI	获取价格	2.5V / 3.3V ECL ±2, ±4, ±8 Clock Generation C

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