Datasheet > CY2PD817

CY2PD817

更新时间： 2024-11-20 03:12:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
6页	59K
描述
320-MHz 1:7 PECL to PECL/CMOS Buffer

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY2PD817 数据手册

CY2PD817

320-MHz 1:7 PECL to PECL/CMOS Buffer

Features

Description

• DC to 320-MHz operation

• 50-ps output-output skew

The CY2PD817 is a low-voltage LVPECL-to-LVPECL and

LVCMOS fanout buffer designed for servers, data communi-

cations, and clock management.

• 30-ps cycle-cycle jitter

The CY2PD817 is ideal for applications requiring mixed differ-

ential and single-ended clock distribution. This device accepts

an LVPECL input reference clock and provides one LVPECL

and six LVCMOS/LVTTL output clocks. The outputs are parti-

tioned into three banks of one, two, and four outputs. The

LVPECL output is a buffered copy of the input clock while the

LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is

set HIGH, the output dividers are set to 1. In this mode, the

maximum input frequency is limited to 250 MHz.

• 2.5V power supply

• LVPECL input @ 320-MHz Operation

• One LVPECL output @ 320-MHz Operation

• Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz

• Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz

• 45% to 55% output duty cycle

• Output divider control

• Output enable/disable control

• Operating temperature range: 0°C to +85°C

• 24-pin TSSOP

When OE is set HIGH, the outputs are disabled in a High-Z

state.

Block Diagram

Pin Configuration

VDD

QA0

QA1

VDD

PCLKI

PCLKO

VSS

VDD

PCLKO

VDD

PCLKO

÷ 4, ÷ 1

÷ 2, ÷ 1

QB0

QB1

VSS

VDD

QB2

QB3

VSS

PCLKI

QA[0:1]

PCLKO

VSS

QB[0:3]

VDD

CLRDIV

VSS

CLRDIV

24 TSSOP

Cypress Semiconductor Corporation

Document #: 38-07574 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 28, 2003

12 3 4 5 6

中文翻译

下载PDF

与CY2PD817相关器件

型号	品牌	获取价格	描述	数据表
CY2PD817ZC	CYPRESS	获取价格	320-MHz 1:7 PECL to PECL/CMOS Buffer
CY2PD817ZCT	CYPRESS	获取价格	320-MHz 1:7 PECL to PECL/CMOS Buffer
CY2PP3115	CYPRESS	获取价格	1:15 Differential Fanout Buffer
CY2PP3115AI	CYPRESS	获取价格	1:15 Differential Fanout Buffer
CY2PP3115AIT	CYPRESS	获取价格	1:15 Differential Fanout Buffer
CY2PP3115AXI	CYPRESS	获取价格	Low Skew Clock Driver, 2PP Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 1
CY2PP3115AXIT	CYPRESS	获取价格	Low Skew Clock Driver, 2PP Series, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 1
CY2PP318	ETC	获取价格	Clocks and Buffers
CY2PP318JIT	CYPRESS	获取价格	Low Skew Clock Driver, 2PP Series, 8 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC
CY2PP3210	CYPRESS	获取价格	Dual 1:5 Differential Clock / Data Fanout Buffer