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CY2PP3115AI

更新时间： 2024-11-20 03:12:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路
页数 文件大小 规格书
12页 247K
描述
1:15 Differential Fanout Buffer

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中文翻译

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CY2PP3115AI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：52Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.53
Is Samacsys：N其他特性：ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V
系列：2PP输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G52JESD-609代码：e0
长度：10 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：52
实输出次数：15最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：235
传播延迟（tpd）：1.2 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.06 ns座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

CY2PP3115AI 数据手册

 浏览型号CY2PP3115AI的Datasheet PDF文件第2页浏览型号CY2PP3115AI的Datasheet PDF文件第3页浏览型号CY2PP3115AI的Datasheet PDF文件第4页浏览型号CY2PP3115AI的Datasheet PDF文件第5页浏览型号CY2PP3115AI的Datasheet PDF文件第6页浏览型号CY2PP3115AI的Datasheet PDF文件第7页 
FastEdge™ Series  
CY2PP3115  
PRELIMINARY  
1:15 Differential Fanout Buffer  
Features  
Description  
The CY2PP3115 is a low-skew, low propagation delay 1-to-15  
differential fanout buffer targeted to meet the requirements of  
high-performance clock and data distribution applications. The  
device is implemented on SiGe technology and has a fully  
differential internal architecture that is optimized to achieve  
low-signal skews at operating frequencies of up to 1.5 GHz.  
• Fifteen ECL/PECL differential outputs grouped in four  
banks  
• Two ECL/PECLdifferential inputs  
• Hot-swappable/-insertable  
• 50-ps output-to-output skew  
• < 200-ps device-to-device skew  
• Less than 2-pS intrinsic jitter  
• < 500-ps propagation delay (typical)  
• Operation up to 1.5 GHz  
The device features two differential input paths which are  
multiplexed internally. This mux is controlled by the CLK_SEL  
pin. The CY2PP3115 may function not only as a differential  
clock buffer but also as a signal level translator and fanout on  
ECL/PECL single-ended signal to 15 ECL/PECL differential  
loads. An external bias pin, VBB, is provided for this purpose.  
In such an application, the VBB pin should be connected to  
either one of the CLKA# or CLKB# inputs and bypassed to VCC  
via a 0.01-µF capacitor.  
Since the CY2PP3115 introduces negligible jitter to the timing  
budget, it is the ideal choice for distributing high frequency,  
high precision clocks across back-planes and boards in  
communication systems. Furthermore, advanced circuit  
design schemes, such as internal temperature compensation,  
ensure that the CY2PP3115 delivers consistent, guaranteed  
performance over differing platforms.  
• PECL mode supply range: VCC = 2.375V to 3.465V with  
VEE = 0V  
• ECL mode supply range: VEE = –2.375V to –3.465V with  
VCC = 0V  
• Industrial temperature range: –40°C to 85°C  
• 52-pin 1.4mm TQFP package  
• Temperature compensation like 100K ECL  
Block Diagram  
Pin Configuration  
FSELA  
QAO  
QA1  
0
VEE  
VCC  
1
CLK0  
CLK0#  
QBO  
/1  
/2  
0
0
39  
38  
37  
36  
35  
34  
33  
32  
VCC  
QC0  
QC0#  
QC1  
QC1#  
QC2  
1
2
3
4
5
6
7
8
VCC  
MR  
FSELA  
FSELB  
CLK0  
CLK0#  
CLK_SEL  
CLK1  
QB1  
QB2  
VEE  
VCC  
1
1
CLK1  
CLK1#  
QC0  
QC1  
VEE  
QC2#  
QC3  
CY2PP3115  
CLK_SEL  
0
1
VEE  
31  
30  
29  
28  
27  
QC3#  
VCC  
NC  
NC  
VCC  
9
CLK1#  
VBB  
FSELC  
FSELD  
VEE  
QC2  
QC3  
10  
11  
12  
13  
FSELB  
FSELC  
QD0  
QD1  
VEE  
MR  
VEE  
0
QD2  
1
QD3  
QD4  
FSELD  
VEE  
QD5  
VBB  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07502 Rev.*A  
Revised November 18, 2003  
1234567...12

中文翻译

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