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CY2LL843

更新时间： 2024-11-20 02:57:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		复用器中继器驱动
页数	文件大小	规格书
13页	262K
描述
High-drive Two-Channel LVDS Repeater/Mux

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中文翻译

获取价格

数据手册

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CY2LL843 数据手册

ComLink™ Series

CY2LL843

High-drive Two-Channel LVDS Repeater/Mux

achieve signaling rates of 700Mbs. The receiver outputs can

be switched to either or both drivers through the multiplexer

Features

• ANSI TIA/EIA-644-1995-compliant

control signals S0/S1. This provides flexibility in application for

either a splitter or router configuration with a single device.

• Designed for data rates to > 700 Mbs = (350 MHz)

• Single 2 × 2 with high-drive output drivers

The Cypress CY2LL843 are configured as

two-channel repeater/Mux.

a single

• Low -voltage differential signaling with output voltages

of ± 350 mV into 50-ohm load version (Bus LVDS)

The LVDS standard provides a minimum differential output

voltage of 247 mV into a 50-ohm load and receipt of as little as

100 mV signals with up to 1V of DC offset between transmitter

and receiver. The Cypress CY2LL843 doubles the output drive

current to achieve BusLVDS signaling levels with a faster

rise/fall times into 50-ohm load.

• Single 3.3V supply

• Accepts ± 350-mV differential inputs

• Output Drivers are high-impedance when disabled or

when V_DD≤1.5V

• 16-pin SOIC/TSSOP packages

• Industrial version available

A doubly terminated BusLVDS line enables multipoint config-

urations.

Description

Designed for both point to point based-band multi-point data

transmission over controlled impedance lines.

The Cypress CY2LL843 are differential line drivers and

receivers that utilize Low Voltage Signaling or LVDS, to

Block Diagram

Pin Configuration

VDD

1DE

VDD

GND

2DE

S0 S1

1DE

2DE

GND

16 pin SOIC/TSSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07066 Rev. OBS

Revised December 02, 2004

12 3 4 5 6 7...13

中文翻译

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