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CY2LL8423ZC PDF预览

CY2LL8423ZC

更新时间: 2024-11-20 14:50:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
11页 186K
描述
Line Transceiver, 4 Func, 4 Driver, 4 Rcvr, PDSO28, 4.40 MM, TSSOP-28

CY2LL8423ZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:4.40 MM, TSSOP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.9差分输出:YES
驱动器位数:4输入特性:DIFFERENTIAL
接口集成电路类型:LINE TRANSCEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:9.7 mm功能数量:4
端子数量:28最高工作温度:70 °C
最低工作温度:最小输出摆幅:0.247 V
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.53,22封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
最大接收延迟:6 ns接收器位数:4
座面最大高度:1.1 mm子类别:Line Driver or Receivers
最大压摆率:54 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:6 ns
宽度:4.4 mmBase Number Matches:1

CY2LL8423ZC 数据手册

 浏览型号CY2LL8423ZC的Datasheet PDF文件第2页浏览型号CY2LL8423ZC的Datasheet PDF文件第3页浏览型号CY2LL8423ZC的Datasheet PDF文件第4页浏览型号CY2LL8423ZC的Datasheet PDF文件第5页浏览型号CY2LL8423ZC的Datasheet PDF文件第6页浏览型号CY2LL8423ZC的Datasheet PDF文件第7页 
8423  
COMLINK™ SERIES  
CY2LL8423  
High Drive Dual 2-Channel LVDS Repeater/Mux  
Features  
Description  
ANSI TIA/EIA-644-1995 compliant  
Designed for data rates to > 650 Mbps = (325 MHz)  
Single 2x2 with high drive output drivers  
The Cypress CY2LL8423 are differential line drivers and re-  
ceivers that utilize Low Voltage Signaling or LVDS, to achieve  
signaling rates of 650 Mbps. The receiver outputs can be  
switched to either or both drivers through the multiplexer con-  
trol signals S2/S3. This provides flexibility in application for  
either a splitter or router configuration with a single device.  
Low Voltage Differential Signaling with output volt-  
ages of ± 350 mV into 50-ohm load version (Bus  
LVDS)  
The Cypress CY2LL8423 are configured as a dual 2-channel  
repeater/Mux. The LVDS standard provides a minimum dif-  
ferential output voltage of 247 mV into a 50-ohm load and  
receipt of as little as 100 mV signals with up to 1 Volt of DC  
offset between transmitter and receiver.  
Single 3.3V supply  
Accepts ±350 mV differential inputs  
Output drivers are high impedance when disabled or  
when VDD <1.5V  
28-pin SSOP/TSSOP packages  
Industrial version available  
A doubly terminated BusLVDS line enables multipoint config-  
urations.  
Designed for both point-to-point based-band multipoint data  
transmission over controlled impedance lines.  
Block Diagram  
Pin Configuration  
1DE  
4
2
1
27  
26  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
1Y  
1A  
1B  
1B  
1A  
1
2
3
4
5
6
7
8
1Y  
1Z  
1Z  
2DE  
2Z  
S0  
1DE  
S1  
6
2A  
2B  
23  
24  
2Y  
2Z  
7
2Y  
25  
2A  
2B  
GND  
VDD  
2DE  
3
5
3A  
S0S1  
3Y  
9
3B  
3DE  
3Z  
4DE  
4Y  
10  
11  
12  
13  
14  
S2  
11  
3DE  
S3  
8
9
20  
19  
3A  
3Y  
3Z  
4Z  
3B  
4A  
4B  
GND  
13  
14  
17  
16  
4A  
4B  
4Y  
4Z  
28 pin TSSOP/SSOP  
18  
4DE  
10  
12  
S2 S3  
Cypress Semiconductor Corporation  
Document #: 38-07065 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised July 3, 2002  

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