Datasheet > CY14B512P_12

CY14B512P_12

更新时间： 2024-09-13 12:50:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器时钟
页数	文件大小	规格书
34页	1860K
描述
512-Kbit (64 K Ã 8) Serial (SPI) nvSRAM with Real Time Clock

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中文翻译

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CY14B512P_12 数据手册

CY14B512P

512-Kbit (64 K × 8) Serial (SPI) nvSRAM

with Real Time Clock

512-Kbit (64

K × 8) Serial (SPI) nvSRAM with Real Time Clock

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

Features

■ 512-Kbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 64 K × 8

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4, 1/2, or entire array

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by the user

using HSB pin (Hardware STORE) or SPI instruction

(Software STORE)

■ Low power consumption

❐ Single 3 V + 20%, –10% operation

❐ Average active current of 10 mA at 40 MHz operation

❐ RECALL to SRAM initiated on power-up (Power-Up

RECALL) or by serial peripheral interface (SPI) instruction

(Software RECALL)

■ Industry standard configurations

❐ Industrial temperature

❐ 16-pin small outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

❐ Automatic STORE on power-down with a small capacitor

■ High reliability

Overview

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years

The Cypress CY14B512P combines a 512-Kbit nvSRAM^[1]with

a full-featured real time clock in a monolithic integrated circuit

with serial SPI interface. The memory is organized as 64 K words

of 8 bits each. The embedded nonvolatile elements incorporate

the QuantumTrap technology, creating the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while the QuantumTrap cells provide highly reliable

nonvolatile storage of data. Data transfers from SRAM to the

nonvolatile elements (STORE operation) takes place

automatically at power-down. On power-up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

The STORE and RECALL operations can also be initiated by the

user through SPI instruction.

■ Real time clock (RTC)

❐ Full featured RTC

❐ Watchdog timer

❐ Clock alarm with programmable interrupts

❐ Capacitor or battery backup for RTC

❐ Backup current of 0.35 µA (typical)

■ High-speed SPI

❐ 40 MHz clock rate – SRAM memory access

❐ 25 MHz clock rate – RTC memory access

❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)

Logic Block Diagram

V_CC

V_CAP

QuantumTrap

64 K X 8

Power Control

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM Array

HOLD

RECALL

64 K X 8

Instruction

D0-D7

A0-A15

out

Address

Decoder

RTC

INT

MUX

Data I/O register

Status Register

Note

1. This device is referred to as nvSRAM throughout the document.

Cypress Semiconductor Corporation

Document Number: 001-53872 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 13, 2012

12 3 4 5 6 7...34

中文翻译

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与CY14B512P_12相关器件

型号	品牌	获取价格	描述	数据表
CY14B512P_13	CYPRESS	获取价格	512-Kbit (64 K x 8) Serial (SPI) nvSRAM with Real Time Clock
CY14B512PA	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC
CY14B512PA-SFXI	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC
CY14B512PA-SFXIT	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC
CY14B512P-SFXI	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM with
CY14B512P-SFXIT	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM with
CY14B512Q	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM Infinite read, write, and RECALL cycles
CY14B512Q1	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM
CY14B512Q1_12	CYPRESS	获取价格	512-Kbit (64 K Ã 8) Serial (SPI) nvSRAM
CY14B512Q1_13	CYPRESS	获取价格	512-Kbit (64 K x 8) Serial (SPI) nvSRAM

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