CY14C064I
CY14B064I
CY14E064I
64-Kbit (8 K × 8) Serial (I2C) nvSRAM
with Real Time Clock
64-Kbit (8
K × 8) Serial (I2C) nvSRAM with Real Time Clock
■ I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
Features
■ 64-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 8 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) orHSB pin (Hardware STORE)
■ Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 250 µA
❐ Sleep mode current of 8 µA
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
■ High reliability
■ Industry standard configurations
❐ Operating voltages:
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ Real Time Clock (RTC)
❐ Full-featured RTC
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 µA (typical)
■ High-speed I2C interface [1]
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast mode Plus 1 MHz speed
❐ High speed: 3.4 MHz
• CY14C064I: VCC = 2.4 V to 2.6 V
• CY14B064I: VCC = 2.7 V to 3.6 V
• CY14E064I: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C064I/CY14B064I/CY14E064I combines a
64-Kbit nvSRAM[2] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 8 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for one-quarter, one-half, or entire
array
Logic Block Diagram
Serial Number
VRTCcap
VCC VCAP
VRTCbat
Manufacturer ID /
Product ID
Power Control
Block
Memory Control Register
Command Register
QuantumTrap
8 K x 8
Sleep
STORE
Control Registers Slave
SDA
SCL
A2, A1, A0
WP
I2C Control Logic
Slave Address
Decoder
SRAM
8 K x 8
Memory
Address and Data
Control
RECALL
Memory Slave
RTC Slave
Xin
RTC Control Logic
INT/SQW
Xout
Registers
Counters
Notes
2
1. The I C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips
which support only one mode of operation. Refer to AN87209 for more details.
2
2. Serial (I C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document Number: 001-68169 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 30, 2013