CY14C101J2-SXI

更新时间： 2024-11-05 12:20:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	1995K
描述
1 Mbit (128 K Ã 8) Serial (I2C) nvSRAM

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数据手册

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CY14C101J2-SXI 数据手册

CY14C101J

PRELIMINARY

CY14B101J, CY14E101J

1 Mbit (128 K × 8) Serial (I²C) nvSRAM

■ Industry standard configurations

❐ Operating voltages:

• CY14C101J: V_CC= 2.4 V to 2.6 V

• CY14B101J: V_CC= 2.7 V to 3.6 V

• CY14E101J: V_CC= 4.5 V to 5.5 V

❐ Industrial temperature

Features

■ 1-Mbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 128 K × 8

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by using I²C

command (SoftwareSTORE) orHSBpin(HardwareSTORE)

❐ 8- and 16-pin small outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

❐ RECALL to SRAM initiated on power-up (Power-Up RE-

CALL) or by I²C command (Software RECALL)

❐ Automatic STORE on power-down with a small capacitor (ex-

cept for CY14X101J1)

Overview

The Cypress CY14C101J/CY14B101J/CY14E101J combines a

1-Mbit nvSRAM^[1]with a nonvolatile element in each memory

cell. The memory is organized as 128 K words of 8 bits each. The

embedded nonvolatile elements incorporate the QuantumTrap

technology, creating the world’s most reliable nonvolatile

memory. The SRAM provides infinite read and write cycles, while

the QuantumTrap cells provide highly reliable nonvolatile

storage of data. Data transfers from SRAM to the nonvolatile

elements (STORE operation) takes place automatically at

power-down (except for CY14X101J1). On power-up, data is

restored to the SRAM from the nonvolatile memory (RECALL

operation). The STORE and RECALL operations can also be

initiated by the user through I²C commands.

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years at 85 °C

■ High speed I²C interface

❐ Industry standard 100 kHz and 400 kHz speed

❐ Fast-mode Plus: 1 MHz speed

❐ High speed: 3.4 MHz

❐ Zero cycle delay reads and writes

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

❐ Software block protection for 1/4, 1/2, or entire array

■ I²C access to special functions

❐ Nonvolatile STORE/RECALL

❐ 8 byte serial number

Configuration

Feature

CY14X101J1

CY14X101J2

CY14X101J3

AutoStore

Yes

❐ Manufacturer ID and Product ID

❐ Sleep mode

Software

STORE

Yes

■ Low power consumption

Hardware

STORE

Yes

❐ Average active current of 1 mA at 3.4 MHz operation

❐ Average standby mode current of 150 uA

❐ Sleep mode current of 8 uA

Logic Block Diagram

Serial Number

8 x 8

V_CCV_CAP

Manufacture ID/

Product ID

Power Control

Block

Memory Control Register

Command Register

Quantrum Trap

128 K x 8

Sleep

STORE

SRAM

128 K x 8

Control Registers Slave

Memory Slave

SDA

SCL

A2, A1

I²C Control Logic

Slave Address

Decoder

Memory

Address and Data

Control

RECALL

Note

1. Serial (I C) nvSRAM is referred to as nvSRAM throughout the datasheet.

Cypress Semiconductor Corporation

Document #: 001-54050 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 19, 2011

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与CY14C101J2-SXI相关器件

型号	品牌	获取价格	描述	数据表
CY14C101J2-SXIT	CYPRESS	获取价格	1 Mbit (128 K Ã 8) Serial (I2C) nvSRAM
CY14C101J3-SFXI	CYPRESS	获取价格	1 Mbit (128 K Ã 8) Serial (I2C) nvSRAM
CY14C101J3-SFXIT	CYPRESS	获取价格	1 Mbit (128 K Ã 8) Serial (I2C) nvSRAM
CY14C101PA	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM with Real Time Clock
CY14C101PA_1105	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM with Real Time Clock
CY14C101PA_12	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Serial (SPI) nvSRAM with
CY14C101PA_13	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM with Real Time Clock
CY14C101PA-SF104XI	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Serial (SPI) nvSRAM with
CY14C101PA-SF104XIT	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Serial (SPI) nvSRAM with
CY14C101PA-SFXI	CYPRESS	获取价格	1-Mbit (128 K Ã 8) Serial (SPI) nvSRAM with

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