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CY14C256PA_12 PDF预览

CY14C256PA_12

更新时间: 2024-09-16 12:50:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
43页 1172K
描述
256-Kbit (32 K × 8) SPI nvSRAM with Real Time Clock

CY14C256PA_12 数据手册

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CY14C256PA  
CY14B256PA  
CY14E256PA  
256-Kbit (32 K × 8) SPI nvSRAM  
with Real Time Clock  
256-Kbit (32  
K × 8) SPI nvSRAM with Real Time Clock  
Manufacturer ID and Product ID  
Sleep mode  
Features  
256-Kbit nonvolatile static random access memory (nvSRAM)  
Internally organized as 32 K × 8  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by using SPI  
instruction (Software STORE) or HSB pin (Hardware  
STORE)  
Write protection  
Hardware protection using Write Protect (WP) pin  
Software protection using Write Disable instruction  
Software block protection for 1/4, 1/2, or entire array  
Low power consumption  
Average active current of 3 mA at 40 MHz operation  
Average standby mode current of 250 A  
Sleep mode current of 8 A  
RECALL to SRAM initiated on power-up (Power-Up  
RECALL) or by SPI instruction (Software RECALL)  
Automatic STORE on power-down with a small capacitor  
High reliability  
Industry standard configurations  
Operating voltages:  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
Data retention: 20 years at 85C  
Real time clock (RTC)  
Full-featured RTC  
Watchdog timer  
Clock alarm with programmable interrupts  
Backup power fail indication  
Square wave output with programmable frequency (1 Hz,  
512 Hz, 4096 Hz, 32.768 kHz)  
• CY14C256PA: VCC = 2.4 V to 2.6 V  
• CY14B256PA: VCC = 2.7 V to 3.6 V  
• CY14E256PA: VCC = 4.5 V to 5.5 V  
Industrial temperature  
16-pin small outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
Overview  
The Cypress CY14X256PA combines a 256-Kbit nvSRAM[1] with  
a full-featured RTC in a monolithic integrated circuit with serial  
SPI interface. The memory is organized as 32 K words of 8 bits  
each. The embedded nonvolatile elements incorporate the  
QuantumTrap technology, creating the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while the QuantumTrap cells provide highly reliable  
nonvolatile storage of data. Data transfers from SRAM to the  
nonvolatile elements (STORE operation) takes place  
automatically at power-down. On power-up, data is restored to  
the SRAM from the nonvolatile memory (RECALL operation).  
You can also initiate the STORE and RECALL operations  
through SPI instruction.  
Capacitor or battery backup for RTC  
Backup current of 0.45 µA (typical)  
40 MHz and 104 MHz High-speed serial peripheral interface  
(SPI)  
40 MHz clock rate SPI write and read with zero cycle delay  
104 MHz clock rate SPI write and read (with special fast read  
instructions)  
Supports SPI mode 0 (0,0) and mode 3 (1,1)  
SPI access to special functions  
Nonvolatile STORE/RECALL  
8-byte serial number  
VRTCcap VRTCbat  
VCC VCAP  
Logic Block Diagram  
Serial Number  
8 x 8  
Power Control  
Block  
Manufacturer ID /  
Product ID  
QuantumTrap  
32 K x 8  
SLEEP  
STORE  
RECALL  
SRAM  
32 K x 8  
RDSN/WRSN/RDID  
READ/WRITE  
SI  
CS  
Memory  
Data &  
Address  
Control  
SPI Control Logic  
Write Protection  
Instruction decoder  
STORE/RECALL/ASENB/ASDISB  
SCK  
WP  
SO  
WRSR/RDSR/WREN  
RDRTC/WRTC  
Status Register  
Xin  
RTC Control Logic  
Registers  
INT/SQW  
Xout  
Counters  
Note  
1. This device will be referred to as nvSRAM throughout the document.  
Cypress Semiconductor Corporation  
Document Number: 001-65281 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2012  

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