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CY14C512I

更新时间: 2024-11-24 09:41:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
41页 1809K
描述
512-Kbit (64 K x 8) Serial (I2C) nvSRAM with Real Time Clock

CY14C512I 数据手册

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CY14C512I  
CY14B512I, CY14E512I  
512-Kbit (64 K × 8) Serial (I2C) nvSRAM  
with Real Time Clock  
512-Kbit (64  
K × 8) Serial (I2C) nvSRAM with Real Time Clock  
I2C access to special functions  
Nonvolatile STORE/RECALL  
8-byte serial number  
Manufacturer ID and Product ID  
Sleep mode  
Features  
512-Kbit nonvolatile static random access memory (nvSRAM)  
Internally organized as 64 K × 8  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by using I2C  
command (Software STORE) orHSB pin (Hardware STORE)  
Low power consumption  
Average active current of 1 mA at 3.4 MHz operation  
Average standby mode current of 250 µA  
Sleep mode current of 8 µA  
RECALL to SRAM initiated on power-up (Power-Up  
RECALL) or by I2C command (Software RECALL)  
Automatic STORE on power-down with a small capacitor  
Industry standard configurations  
Operating voltages:  
• CY14C512I : VCC = 2.4 V to 2.6 V  
• CY14B512I : VCC = 2.7 V to 3.6 V  
• CY14E512I : VCC = 4.5 V to 5.5 V  
Industrial temperature  
High reliability  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
Data retention: 20 years at 85 C  
Real Time Clock (RTC)  
Full-featured RTC  
Watchdog timer  
Clock alarm with programmable interrupts  
Backup power fail indication  
16-pin small outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
Overview  
Square wave output with programmable frequency (1 Hz,  
512 Hz, 4096 Hz, 32.768 kHz)  
The Cypress CY14C512I/CY14B512I/CY14E512I combines a  
512-Kbit nvSRAM[1] with a full-featured RTC in a monolithic  
integrated circuit with serial I2C interface. The memory is  
organized as 64 K words of 8 bits each. The embedded  
nonvolatile elements incorporate the QuantumTrap technology,  
creating the world’s most reliable nonvolatile memory. The  
SRAM provides infinite read and write cycles, while the  
QuantumTrap cells provide highly reliable nonvolatile storage of  
data. Data transfers from SRAM to the nonvolatile elements  
(STORE operation) takes place automatically at power-down.  
On power-up, data is restored to the SRAM from the nonvolatile  
memory (RECALL operation). The STORE and RECALL  
operations can also be initiated by the user through I2C  
commands.  
Capacitor or battery backup for RTC  
Backup current of 0.45 µA (typical)  
High-speed I2C interface  
Industry standard 100 kHz and 400 kHz speed  
Fast mode Plus 1 MHz speed  
High speed 3.4 MHz  
Zero cycle delay reads and writes  
Write protection  
Hardware protection using Write Protect (WP) pin  
Software block protection for one-quarter, one-half, or entire  
array  
Logic Block Diagram  
Serial Number  
8 x 8  
VRTCcap  
VCC VCAP  
VRTCbat  
Manufacture ID/  
Product ID  
Power Control  
Block  
Memory Control Register  
Command Register  
Quantrum Trap  
64 K x 8  
Sleep  
STORE  
SRAM  
64 K x 8  
Control Registers Slave  
SDA  
SCL  
A2, A1, A0  
WP  
I2C Control Logic  
Slave Address  
Decoder  
Memory  
Address and Data  
Control  
RECALL  
Memory Slave  
RTC Slave  
Xin  
RTC Control Logic  
INT/SQW  
Xout  
Registers  
Counters  
Note  
1. Serial (I C) nvSRAM will be referred to as nvSRAM throughout the datasheet.  
2
Cypress Semiconductor Corporation  
Document #: 001-64879 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 4, 2011  
[+] Feedback  

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