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CY14C512Q_12 PDF预览

CY14C512Q_12

更新时间: 2024-09-16 12:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
32页 1515K
描述
512-Kbit (64 K × 8) SPI nvSRAM

CY14C512Q_12 数据手册

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CY14C512Q  
CY14B512Q  
CY14E512Q  
512-Kbit (64 K × 8) SPI nvSRAM  
512-Kbit (64  
K × 8) SPI nvSRAM  
Industry standard configurations  
Operating voltages:  
Features  
512-Kbit nonvolatile static random access memory (nvSRAM)  
• CY14C512Q: VCC = 2.4 V to 2.6 V  
• CY14B512Q: VCC = 2.7 V to 3.6 V  
• CY14E512Q: VCC = 4.5 V to 5.5 V  
Industrial temperature  
8- and 16-pin small outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
internally organized as 64 K × 8  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by using SPI  
instruction (Software STORE) or HSB pin (Hardware  
STORE)  
RECALL to SRAM initiated on power-up (Power-Up  
RECALL) or by SPI instruction (Software RECALL)  
Functional Overview  
Support automatic STORE on power-down with a small  
capacitor (except for CY14X512Q1A)  
The Cypress CY14X512Q combines a 512-Kbit nvSRAM[1] with  
a nonvolatile element in each memory cell with serial SPI  
interface. The memory is organized as 64 K words of 8 bits each.  
The embedded nonvolatile elements incorporate the  
QuantumTrap technology, creating the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while the QuantumTrap cells provide highly reliable  
nonvolatile storage of data. Data transfers from SRAM to the  
nonvolatile elements (STORE operation) takes place automati-  
cally at power-down (except for CY14X512Q1A). On power-up,  
data is restored to the SRAM from the nonvolatile memory  
(RECALL operation). You can also initiate the STORE and  
RECALL operations through SPI instruction.  
High reliability  
Infinite read, write, and RECALL cycles  
1million STORE cycles to QuantumTrap  
Data retention: 20 years at 85 C  
40-MHz, and 104-MHz High-speed serial peripheral interface  
(SPI)  
40-MHz clock rate SPI write and read with zero cycle delay  
104-MHz clock rate SPI write and SPI read (with special fast  
read instructions)  
Supports SPI mode 0 (0,0) and mode 3 (1,1)  
SPI access to special functions  
Nonvolatile STORE/RECALL  
8-byte serial number  
Configuration  
Feature CY14X512Q1A CY14X512Q2A CY14X512Q3A  
Manufacturer ID and Product ID  
Sleep mode  
AutoStore  
No  
Yes  
Yes  
Yes  
Yes  
Write protection  
Software  
STORE  
Yes  
Hardware protection using Write Protect (WP) pin  
Software protection using Write Disable instruction  
Software block protection for 1/4, 1/2, or entire array  
Hardware  
STORE  
No  
No  
Yes  
Low power consumption  
Average active current of 3 mA at 40 MHz operation  
Average standby mode current of 150 A  
Sleep mode current of 8 A  
Logic Block Diagram  
VCC VCAP  
Serial Number  
8 x 8  
Power Control  
Block  
Manufacturer ID /  
Product ID  
QuantumTrap  
64 K x 8  
SLEEP  
STORE  
SRAM  
64 K x 8  
RDSN/WRSN/RDID  
READ/WRITE  
STORE/RECALL/ASENB/ASDISB  
SI  
CS  
Memory  
Data &  
Address  
Control  
RECALL  
SPI Control Logic  
Write Protection  
Instruction decoder  
SCK  
WP  
SO  
WRSR/RDSR/WREN  
Status Register  
Note  
1. This device will be referred to as nvSRAM throughout the document.  
Cypress Semiconductor Corporation  
Document Number: 001-65267 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2012  

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