Datasheet > CY14C512J

CY14C512J

更新时间： 2024-11-20 09:41:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	1505K
描述
512-Kbit (64 K x 8) Serial (I2C) nvSRAM Infinite read, write, and RECALL cycles

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CY14C512J 数据手册

CY14C512J

CY14B512J, CY14E512J

512-Kbit (64 K × 8) Serial (I²C) nvSRAM

512-Kbit (64

K × 8) Serial (I²C) nvSRAM

■ Industry standard configurations

❐ Operating voltages:

Features

■ 512-Kbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 64 K × 8

• CY14C512J: V_CC= 2.4 V to 2.6 V

• CY14B512J: V_CC= 2.7 V to 3.6 V

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by using I²C

command (SoftwareSTORE) orHSBpin(HardwareSTORE)

• CY14E512J: V_CC= 4.5 V to 5.5 V

❐ Industrial temperature

❐ 8- and 16-pin small outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

❐ RECALL to SRAM initiated on power-up (Power-Up

RECALL) or by I²C command (Software RECALL)

Overview

❐ Automatic STORE on power-down with a small capacitor

(except for CY14X512J1)

The Cypress CY14C512J/CY14B512J/CY14E512J combines a

512-Kbit nvSRAM^[1]with a nonvolatile element in each memory

cell. The memory is organized as 64 K words of 8 bits each. The

embedded nonvolatile elements incorporate the QuantumTrap

technology, creating the world’s most reliable nonvolatile

memory. The SRAM provides infinite read and write cycles, while

the QuantumTrap cells provide highly reliable nonvolatile

storage of data. Data transfers from SRAM to the nonvolatile

elements (STORE operation) takes place automatically at

power-down (except for CY14X512J1). On power-up, data is

restored to the SRAM from the nonvolatile memory (RECALL

operation). The STORE and RECALL operations can also be

initiated by the user through I²C commands.

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years at 85 C

■ High speed I²C interface

❐ Industry standard 100 kHz and 400 kHz speed

❐ Fast-mode Plus: 1 MHz speed

❐ High speed: 3.4 MHz

❐ Zero cycle delay reads and writes

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

❐ Software block protection for one-quarter, one-half, or entire

array

Configuration

Feature

AutoStore

CY14X512J1 CY14X512J2 CY14X512J3

■ I²C access to special functions

❐ Nonvolatile STORE/RECALL

❐ 8 byte serial number

❐ Manufacturer ID and Product ID

❐ Sleep mode

Yes

Software STORE

Hardware STORE

Yes

Slave Address pins A2, A1, A0

A2, A1

A2, A1, A0

■ Low power consumption

❐ Average active current of 1 mA at 3.4 MHz operation

❐ Average standby mode current of 150 µA

❐ Sleep mode current of 8 µA

Logic Block Diagram

Serial Number

8 x 8

V_CCV_CAP

Manufacture ID/

Product ID

Power Control

Block

Memory Control Register

Command Register

Quantrum Trap

64 K x 8

Sleep

STORE

SRAM

64 K x 8

Control Registers Slave

Memory Slave

SDA

SCL

A2, A1, A0

I²C Control Logic

Slave Address

Decoder

Memory

Address and Data

Control

RECALL

Note

1. Serial (I C) nvSRAM is referred to as nvSRAM throughout the datasheet.

Cypress Semiconductor Corporation

Document #: 001-65232 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 4, 2011

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与CY14C512J相关器件

型号	品牌	获取价格	描述	数据表
CY14C512J_12	CYPRESS	获取价格	512-Kbit (64 K Ã 8) Serial (I2C) nvSRAM
CY14C512J_13	CYPRESS	获取价格	512-Kbit (64 K x 8) Serial (I2C) nvSRAM
CY14C512PA	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC
CY14C512PA_12	CYPRESS	获取价格	512-Kbit (64 K Ã 8) SPI nvSRAM with Real Tim
CY14C512PA_13	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM
CY14C512Q	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM Infinite read, write, and RECALL cycles
CY14C512Q_12	CYPRESS	获取价格	512-Kbit (64 K Ã 8) SPI nvSRAM
CY14E064I	CYPRESS	获取价格	64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock
CY14E064L	CYPRESS	获取价格	64-Kbit (8K x 8) nvSRAM
CY14E064L_07	CYPRESS	获取价格	64 Kbit (8K x 8) nvSRAM

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