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CY14B512P-SFXIT

更新时间： 2024-11-23 09:41:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
36页 1598K
描述
512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock

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中文翻译

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CY14B512P-SFXIT 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP16,.4
针数：16Reach Compliance Code：compliant
风险等级：5.78JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.285 mm
内存密度：524288 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：16
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：3/3.3 V
认证状态：Not Qualified座面最大高度：2.667 mm
最大待机电流：0.005 A子类别：SRAMs
最大压摆率：0.01 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.4925 mmBase Number Matches：1

CY14B512P-SFXIT 数据手册

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CY14B512P  
512-Kbit (64 K × 8) Serial (SPI) nvSRAM  
with Real Time Clock  
512-Kbit (64  
K × 8) Serial (SPI) nvSRAM with Real Time Clock  
■ Write protection  
❐ Hardware protection using Write Protect (WP) pin  
Features  
■ 512-Kbit nonvolatile static random access memory (nvSRAM)  
❐ Internally organized as 64 K × 8  
❐ Software protection using Write Disable instruction  
❐ Software block protection for 1/4, 1/2, or entire array  
❐ STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by the user  
using HSB pin (Hardware STORE) or SPI instruction  
(Software STORE)  
■ Low power consumption  
❐ Single 3 V + 20%, –10% operation  
❐ Average active current of 10 mA at 40 MHz operation  
❐ RECALL to SRAM initiated on power-up (Power-Up  
RECALL) or by serial peripheral interface (SPI) instruction  
(Software RECALL)  
■ Industry standard configurations  
❐ Industrial temperature  
❐ 16-pin small outline integrated circuit (SOIC) package  
❐ Restriction of hazardous substances (RoHS) compliant  
❐ Automatic STORE on power-down with a small capacitor  
■ High reliability  
Overview  
❐ Infinite read, write, and RECALL cycles  
❐ 1 million STORE cycles to QuantumTrap  
❐ Data retention: 20 years  
The Cypress CY14B512P combines a 512-Kbit nvSRAM[1] with  
a full-featured real time clock in a monolithic integrated circuit  
with serial SPI interface. The memory is organized as 64 K words  
of 8 bits each. The embedded nonvolatile elements incorporate  
the QuantumTrap technology, creating the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while the QuantumTrap cells provide highly reliable  
nonvolatile storage of data. Data transfers from SRAM to the  
nonvolatile elements (STORE operation) takes place  
automatically at power-down. On power-up, data is restored to  
the SRAM from the nonvolatile memory (RECALL operation).  
The STORE and RECALL operations can also be initiated by the  
user through SPI instruction.  
■ Real time clock (RTC)  
❐ Full featured RTC  
❐ Watchdog timer  
❐ Clock alarm with programmable interrupts  
❐ Capacitor or battery backup for RTC  
❐ Backup current of 0.35 µA (typical)  
■ High-speed SPI  
❐ 40 MHz clock rate – SRAM memory access  
❐ 25 MHz clock rate – RTC memory access  
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)  
Logic Block Diagram  
VCC  
VCAP  
QuantumTrap  
64 K X 8  
Power Control  
CS  
WP  
SCK  
Instruction decode  
Write protect  
Control logic  
STORE/RECALL  
Control  
STORE  
HSB  
SRAM Array  
HOLD  
RECALL  
64 K X 8  
Instruction  
register  
D0-D7  
A0-A15  
X
out  
in  
Address  
Decoder  
RTC  
X
INT  
MUX  
Data I/O register  
Status Register  
SO  
SI  
Note  
1. This device is referred to as nvSRAM throughout the document.  
Cypress Semiconductor Corporation  
Document #: 001-53872 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 12, 2011  
[+] Feedback  
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中文翻译

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