Datasheet > CY14B512Q1_12

CY14B512Q1_12

更新时间： 2024-11-23 12:50:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
27页	1809K
描述
512-Kbit (64 K Ã 8) Serial (SPI) nvSRAM

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中文翻译

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数据手册

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CY14B512Q1_12 数据手册

CY14B512Q1

CY14B512Q2

CY14B512Q3

512-Kbit (64 K × 8) Serial (SPI) nvSRAM

512-Kbit (64

K × 8) Serial (SPI) nvSRAM

■ Industry standard configurations

❐ Industrial temperature

❐ CY14B512Q1 has identical pin configuration to industry

standard 8-pin NV memory

Features

■ 512-Kbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 64 K × 8

❐ 8-pin dual flat no-lead (DFN) package and 16-pin small

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by user using

HSB pin (hardware STORE) or SPI instruction (Software

STORE)

outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

❐ RECALL to SRAM initiated on power-up (power-Up

Functional Overview

RECALL) or by SPI instruction (software RECALL)

The

Cypress

CY14B512Q1/CY14B512Q2/CY14B512Q3

❐ Automatic STORE on power-down with a small capacitor

(except for CY14B512Q1)

combines a 512-Kbit nvSRAM^[1]with a nonvolatile element in

each memory cell with serial SPI interface. The memory is

organized as 64 K words of 8 bits each. The embedded

nonvolatile elements incorporate the QuantumTrap technology,

creating the world’s most reliable nonvolatile memory. The

SRAM provides infinite read and write cycles, while the

QuantumTrap cell provides highly reliable nonvolatile storage of

data. Data transfers from SRAM to the nonvolatile elements

(STORE operation) takes place automatically at power-down

(except for CY14B512Q1). On power-up, data is restored to the

SRAM from the nonvolatile memory (RECALL operation). The

STORE and RECALL operations can also be initiated by the user

through SPI instruction.

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years

■ High speed serial peripheral interface (SPI)

❐ 40 MHz clock rate

❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4,1/2, or entire array

Configuration

■ Low power consumption

❐ Single 3 V +20%, –10% operation

❐ Average active current of 10 mA at 40 MHz operation

Feature

AutoStore

CY14B512Q1 CY14B512Q2 CY14B512Q3

Yes

Software

STORE

Yes

Hardware

STORE

Yes

V_CC

V_CAP

Logic Block Diagram

QuantumTrap

64 K X 8

Power Control

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM Array

HOLD

RECALL

64 K X 8

Instruction

D0-D7

A0-A15

Address

Decoder

Data I/O register

Status Register

Note

1. This device will be referred to as nvSRAM throughout the document.

Cypress Semiconductor Corporation

Document Number: 001-53873 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 13, 2012

12 3 4 5 6 7...27

中文翻译

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与CY14B512Q1_12相关器件

型号	品牌	获取价格	描述	数据表
CY14B512Q1_13	CYPRESS	获取价格	512-Kbit (64 K x 8) Serial (SPI) nvSRAM
CY14B512Q1A-SXI	CYPRESS	获取价格	512-Kbit (64 K Ã 8) SPI nvSRAM
CY14B512Q1A-SXIT	CYPRESS	获取价格	512-Kbit (64 K Ã 8) SPI nvSRAM
CY14B512Q2	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM
CY14B512Q2A-SXI	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM Infinite read, write, and RECALL cycles
CY14B512Q2A-SXI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B512Q2A-SXIT	CYPRESS	获取价格	512-Kbit (64 K x 8) SPI nvSRAM Infinite read, write, and RECALL cycles
CY14B512Q2A-SXIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B512Q2-LHXI	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM
CY14B512Q3	CYPRESS	获取价格	512-Kbit (64 K × 8) Serial (SPI) nvSRAM

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