CDCVF2509

更新时间： 2024-10-01 22:28:55

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
11页	146K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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CDCVF2509 数据手册

CDCVF2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS637 – DECEMBER 1999

PW PACKAGE

(TOP VIEW)

Designed to Meet and Exceed PC133

SDRAM Registered DIMM Specification

Rev. 1.1

AGND

CLK

Spread Spectrum Clock Compatible

Operating Frequency 50 MHz to 175 MHz

1Y0

1Y1

1Y2

GND

1Y3

Static Phase Error Distribution at 66MHz to

166 MHz is ±125 ps

2Y0

2Y1

GND

2Y2

2Y3

Jitter (cyc – cyc) at 66 MHz to 166 MHz is

|70| ps

Advanced Deep Sub-Micron Process

Results in More Than 40% Lower Power

Consumption Versus Current Generation

PC133 Devices

1Y4

FBOUT

FBIN

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

25-Ω On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at 3.3 V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled

or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in

phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDCVF2509 is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

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CDCVF2509 替代型号

型号	品牌	替代类型	描述	数据表
CDCF2509	TI	功能相似	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509C	TI	功能相似	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509	TI	功能相似	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCVF2509相关器件

型号	品牌	获取价格	描述	数据表
CDCVF2509A	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509APW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2509PWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510A	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APW	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85

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