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CDCVF855

更新时间： 2024-11-20 04:11:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
14页 242K
描述
2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

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CDCVF855 数据手册

 浏览型号CDCVF855的Datasheet PDF文件第2页浏览型号CDCVF855的Datasheet PDF文件第3页浏览型号CDCVF855的Datasheet PDF文件第4页浏览型号CDCVF855的Datasheet PDF文件第5页浏览型号CDCVF855的Datasheet PDF文件第6页浏览型号CDCVF855的Datasheet PDF文件第7页 
CDCVF855  
www.ti.com  
SCAS839A–APRIL 2007–REVISED MAY 2007  
2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER  
FEATURES  
DESCRIPTION  
•
•
•
Spread-Spectrum Clock Compatible  
The CDCVF855 is a high-performance, low-skew,  
low-jitter, zero-delay buffer that distributes  
differential clock input pair (CLK, CLK) to  
a
4
Operating Frequency: 60 MHz to 220 MHz  
Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200  
MHz)  
differential pairs of clock outputs (Y[0:3], Y[0:3]) and  
one differential pair of feedback clock outputs  
(FBOUT, FBOUT). The clock outputs are controlled  
by the clock inputs (CLK, CLK), the feedback clocks  
(FBIN, FBIN), and the analog power input (AVDD).  
When PWRDWN is high, the outputs switch in phase  
and frequency with CLK. When PWRDWN is low, all  
outputs are disabled to a high-impedance state  
(3-state) and the PLL is shut down (low-power  
mode). The device also enters this low-power mode  
when the input frequency falls below a suggested  
detection frequency that is below 20 MHz (typical 10  
MHz). An input frequency-detection circuit detects  
the low-frequency condition and, after applying a  
>20-MHz input signal, this detection circuit turns the  
PLL on and enables the outputs.  
•
•
•
•
•
•
•
•
Low Static Phase Offset: ±50 ps  
Low Jitter (Period): ±60 ps (±30 ps at 200 MHz)  
1-to-4 Differential Clock Distribution (SSTL2)  
Best in Class for VOX = VDD/2 ±0.1 V  
Operates From Dual 2.6-V or 2.5-V Supplies  
Available in a 28-Pin TSSOP Package  
Consumes < 100-µA Quiescent Current  
External Feedback Pins (FBIN, FBIN) Are Used  
to Synchronize the Outputs to the Input  
Clocks  
•
•
•
Meets/Exceeds JEDEC Standard (JESD82-1)  
For DDRI-200/266/333 Specification  
When AVDD is strapped low, the PLL is turned off  
and bypassed for test purposes. The CDCVF855 is  
also able to track spread-spectrum clocking for  
reduced EMI.  
Meets/Exceeds Proposed DDRI-400  
Specification (JESD82-1A)  
Enters Low-Power Mode When No CLK Input  
Signal Is Applied or PWRDWN Is Low  
Because the CDCVF855 is based on PLL circuitry, it  
requires a stabilization time to achieve phase-lock of  
the PLL. This stabilization time is required following  
power up. The CDCVF855 is characterized for both  
commercial and industrial temperature ranges.  
APPLICATIONS  
•
•
DDR Memory Modules (DDR400/333/266/200)  
Zero-Delay Fan-Out Buffer  
AVAILABLE OPTIONS  
TA  
TSSOP (PW)  
–40°C to 85°C  
CDCVF855PW  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
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CDCVF855 替代型号

型号 品牌 替代类型 描述 数据表
CDCV855 TI

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