CDCVF857

更新时间： 2024-11-18 22:28:55

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
19页	473K
描述
2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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数据手册

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CDCVF857 数据手册

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SCAS047D − MARCH 2003 − REVISED JUNE 2005

Recommended Applications:

− DDR Memory Modules

(DDR400/333/266/200)

Operates From Dual 2.6-V or 2.5-V Supplies

Available in a 40-Pin MLF Package, 48-Pin

TSSOP Package, 56-Ball MicroStar Junior

BGA Package

− Zero Delay Fan-Out Buffer

Spread Spectrum Clock Compatible

Operating Frequency: 60 MHz to 220 MHz

Low Jitter (Cycle-Cycle): 35 ps

Low Static Phase Offset: 50 ps

Low Jitter (Period): 30 ps

Consumes < 100-µA Quiescent Current

External Feedback Pins (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

Meets/Exceeds JEDEC Standard

(JESD82−1) For DDRI-200/266/333

Specification

1-To-10 Differential Clock Distribution

(SSTL2)

Meets/Exceeds Proposed DDRI-400

Specification (JESD82−1A)

Best in Class for V

= V /2 0.1 V

OX DD

Enters Low-Power Mode When No CLK

Input Signal Is Applied or PWRDWN Is Low

description

The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock

input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback

clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback

clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, the outputs switch in phase

and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)

and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input

frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input

frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this

detection circuit turns the PLL on and enables the outputs.

When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able

to track spread spectrum clocking for reduced EMI.

Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the

PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial

and industrial temperature ranges.

AVAILABLE OPTIONS

†

TSSOP (DGG)

40-Pin MLF

56-Ball BGA

CDCVF857DGG

(Pb-Free)

−40°C to 85°C

CDCVF857RTB

CDCVF857GQL

CDCVF857RHA

(Pb-Free, Green)

†

Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum T allowed is 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...19

中文翻译

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与CDCVF857相关器件

型号	品牌	获取价格	描述	数据表
CDCVF857DGG	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857DGGG4	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857DGGR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857DGGRG4	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857GQL	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857GQLR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857IDGG	TI	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, MO-153,
CDCVF857IRTB	TI	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40, 6 X 6 MM, 0.5 MM P
CDCVF857RHA	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857RHAR	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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