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CDCVF857DGG PDF预览

CDCVF857DGG

更新时间： 2024-11-19 22:40:31
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
19页 473K
描述
2.5-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDCVF857DGG 数据手册

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SCAS047D − MARCH 2003 − REVISED JUNE 2005  
D
Recommended Applications:  
− DDR Memory Modules  
(DDR400/333/266/200)  
D
Operates From Dual 2.6-V or 2.5-V Supplies  
D
Available in a 40-Pin MLF Package, 48-Pin  
TSSOP Package, 56-Ball MicroStar Junior  
BGA Package  
− Zero Delay Fan-Out Buffer  
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
Operating Frequency: 60 MHz to 220 MHz  
Low Jitter (Cycle-Cycle): 35 ps  
Low Static Phase Offset: 50 ps  
Low Jitter (Period): 30 ps  
D
D
Consumes < 100-µA Quiescent Current  
External Feedback Pins (FBIN, FBIN) Are  
Used to Synchronize the Outputs to the  
Input Clocks  
D
Meets/Exceeds JEDEC Standard  
(JESD82−1) For DDRI-200/266/333  
Specification  
1-To-10 Differential Clock Distribution  
(SSTL2)  
D
D
Meets/Exceeds Proposed DDRI-400  
Specification (JESD82−1A)  
D
Best in Class for V  
= V /2 0.1 V  
OX DD  
Enters Low-Power Mode When No CLK  
Input Signal Is Applied or PWRDWN Is Low  
description  
The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock  
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback  
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback  
clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, the outputs switch in phase  
DD  
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)  
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input  
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input  
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this  
detection circuit turns the PLL on and enables the outputs.  
When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able  
DD  
to track spread spectrum clocking for reduced EMI.  
Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the  
PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial  
and industrial temperature ranges.  
AVAILABLE OPTIONS  
†
T
A
TSSOP (DGG)  
40-Pin MLF  
56-Ball BGA  
CDCVF857DGG  
(Pb-Free)  
−40°C to 85°C  
−40°C to 85°C  
CDCVF857RTB  
CDCVF857GQL  
CDCVF857RHA  
(Pb-Free, Green)  
†
Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum T allowed is 70°C.  
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

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CDCVF857DGG 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF857DGGR TI

完全替代

 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDC857-2DGG TI

类似代替

 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDCV857DGGR TI

类似代替

 2.5-V PHASE LOCK LOOP CLOCK DRIVER

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CDCVF857IDGG TI

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 		PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, MO-153,
CDCVF857IRTB TI

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 		PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40, 6 X 6 MM, 0.5 MM P
CDCVF857RHA TI

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 		2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857RHAR TI

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