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CDC857-2DGG PDF预览

CDC857-2DGG

更新时间： 2024-11-19 22:23:59
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
12页 159K
描述
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

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中文翻译

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CDC857-2DGG 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.28
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：2功能数量：1
反相输出次数：端子数量：48
实输出次数：10最高工作温度：85 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5 V传播延迟（tpd）：6 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.1 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

CDC857-2DGG 数据手册

 浏览型号CDC857-2DGG的Datasheet PDF文件第2页浏览型号CDC857-2DGG的Datasheet PDF文件第3页浏览型号CDC857-2DGG的Datasheet PDF文件第4页浏览型号CDC857-2DGG的Datasheet PDF文件第5页浏览型号CDC857-2DGG的Datasheet PDF文件第6页浏览型号CDC857-2DGG的Datasheet PDF文件第7页 
CDC857-2, CDC857-3  
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS  
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999  
DGG PACKAGE  
(TOP VIEW)  
Phase-Lock Loop Clock Distribution for  
Double Data Rate Synchronous DRAM  
Applications  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
Y0  
GND  
Y5  
Distributes One Differential Clock Input to  
Ten Differential Outputs  
2
3
Y0  
Y5  
External Feedback Pins (FBIN, FBIN) Are  
Used to Synchronize the Outputs to the  
Clock Input  
4
V
V
CC  
Y1  
CC  
5
Y6  
6
Y1  
Y6  
Operates at V  
= 2.5 V and AV  
= 3.3 V  
CC  
CC  
7
GND  
GND  
Y2  
GND  
GND  
Y7  
Packaged in Plastic 48-Pin (DGG) Thin  
Shrink Small-Outline Package (TSSOP)  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Y2  
Y7  
Spread Spectrum Clocking Tracking  
Capability to Reduce EMI  
V
V
V
CC  
CC  
CLK  
CLK  
CC  
G
description  
FBIN  
FBIN  
The CDC857-2 and CDC857-3 are high-perfor-  
mance, low-skew, low-jitter, phase-lock loop  
(PLL) clock driver. They use a PLL to precisely  
align, in both frequency and phase, the feedback  
(FBOUT) output to the clock (CLK) input signal.  
The CDC857-3 operates at 3.3 V (PLL) and 2.5 V  
(output buffer). The CDC857-2 operates at  
2.5 V (PLL and output buffer).  
V
V
CC  
CC  
AGND  
GND  
Y3  
CC  
AV  
FBOUT  
FBOUT  
GND  
Y8  
Y3  
Y8  
V
V
CC  
Y4  
CC  
Y9  
One bank of ten inverting and noninverting  
outputs provide ten low-skew, low-jitter copies of  
CLK. Output signal duty cycles are adjusted to  
50%, independent of the duty cycle at CLK.  
Y4  
Y9  
GND  
GND  
All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs  
switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance  
state (3-state).  
Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for  
the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or  
feedback signals. The PLL can be bypassed for test purposes by strapping AV  
to ground. If AV  
is at GND  
CC  
CC  
and V = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being  
CC  
disabled, after AV  
ramps up to its specified V  
value, with G being kept low. The CDC857 is characterized  
CC  
CC  
for operation from 0°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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CDC857-2DGG 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF857DGGR TI

类似代替

 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857DGG TI

类似代替

 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV857DGGR TI

类似代替

 2.5-V PHASE LOCK LOOP CLOCK DRIVER

与CDC857-2DGG相关器件

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CDC857-2DGGR TI

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 		Phase-Lock Loop Clock Drivers 48-TSSOP
CDC857-2DGGRG4 TI

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 		Phase-Lock Loop Clock Drivers 48-TSSOP
CDC857-3 TI

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 		2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDC857-3DGG ROCHESTER

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 		PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC857-3DGG TI

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 		2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDC857-3DGGG4 TI

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 		PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC857-3DGGR ROCHESTER

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 		PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC906 TI

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 		PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PW TI

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 		PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PWG4 TI

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 		PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

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