CDC913DB

更新时间： 2024-02-28 09:28:40

品牌	Logo	应用领域
德州仪器 - TI		时钟发生器输出元件 PC
页数	文件大小	规格书
10页	155K
描述
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

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CDC913DB 数据手册

CDC913

PC MOTHERBOARD CLOCK GENERATOR

WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

SCAS502C – APRIL 1995 – REVISED MAY 1996

DB OR DW PACKAGE

(TOP VIEW)

Generates Programmable CPU Clock

Output (50 MHz, 60 MHz, or 66 MHz)

Generates 33-MHz Clock for Asynchronous

PCI

AGND

VCC

REFCLK

One 14.318-MHz Reference Clock Output

VCC

2Y1

2Y2

2Y3

All Output Clock Frequencies Derived From

a Single 14.31818-MHz Crystal Input

1Y1

1Y2

LVTTL-Compatible Inputs and Outputs

1Y3

1Y4

GND

CPUCLK

SEL0

Internal Loop Filters for Phase-Lock Loops

Eliminate the Need for External

Components

2Y4

16 GND

PCICLK

SEL1

Operates at 3.3-V V

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages

description

The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock

systemdesignforPCmotherboards. TheCDC913consistsofacrystaloscillator, twophase-lockedloops(PLL),

and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal.

The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0

and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides

a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in

the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input

and buffered out from the PCICLK, CPUCLK, and REFCLK outputs.

Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE. When OE is high, the outputs are in the

high-impedance state. When OE is low, the outputs are enabled.

Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.

This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal

at the X1 input, and following any changes to the SELn inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与CDC913DB相关器件

型号	品牌	获取价格	描述	数据表
CDC913DBLE	TI	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,SSOP,24PIN,PLASTIC
CDC913DW	TI	获取价格	PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS
CDC913DW	ROCHESTER	获取价格	66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24, PLASTIC, SOIC-24
CDC913DWR	ROCHESTER	获取价格	66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24, PLASTIC, SOIC-24
CDC9161DL	ETC	获取价格	CPU System Clock Generator
CDC921	TI	获取价格	133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
CDC921DL	TI	获取价格	133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
CDC922	TI	获取价格	133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
CDC922_06	TI	获取价格	133MHz CLOCK SYNTHESIZER/DRIVER
CDC922DL	TI	获取价格	133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

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