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CDC913DW

更新时间： 2024-11-23 21:54:55
品牌 Logo 应用领域
德州仪器 - TI 晶体时钟发生器微控制器和处理器外围集成电路光电二极管输出元件PC
页数 文件大小 规格书
10页 155K
描述
PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

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中文翻译

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CDC913DW 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SOIC-24针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.81Is Samacsys：N
JESD-30 代码：R-PDSO-G24长度：15.4 mm
端子数量：24最高工作温度：70 °C
最低工作温度：最大输出时钟频率：66 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Clock Generators最大压摆率：1 mA
最大供电电压：3.6 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CDC913DW 数据手册

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CDC913  
PC MOTHERBOARD CLOCK GENERATOR  
WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS  
SCAS502C – APRIL 1995 – REVISED MAY 1996  
DB OR DW PACKAGE  
(TOP VIEW)  
Generates Programmable CPU Clock  
Output (50 MHz, 60 MHz, or 66 MHz)  
Generates 33-MHz Clock for Asynchronous  
PCI  
X1  
X2  
AGND  
A
VCC  
REFCLK  
1
24  
23  
22  
21  
20  
19  
18  
17  
2
One 14.318-MHz Reference Clock Output  
OE  
VCC  
2Y1  
2Y2  
2Y3  
3
All Output Clock Frequencies Derived From  
a Single 14.31818-MHz Crystal Input  
V
4
CC  
1Y1  
1Y2  
5
6
LVTTL-Compatible Inputs and Outputs  
1Y3  
1Y4  
GND  
1A  
CPUCLK  
SEL0  
7
Internal Loop Filters for Phase-Lock Loops  
Eliminate the Need for External  
Components  
2Y4  
8
9
16 GND  
10  
11  
12  
15  
14  
13  
2A  
PCICLK  
SEL1  
Operates at 3.3-V V  
CC  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages  
description  
The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock  
systemdesignforPCmotherboards. TheCDC913consistsofacrystaloscillator, twophase-lockedloops(PLL),  
and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal.  
The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0  
and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides  
a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in  
the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input  
and buffered out from the PCICLK, CPUCLK, and REFCLK outputs.  
Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE. When OE is high, the outputs are in the  
high-impedance state. When OE is low, the outputs are enabled.  
Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.  
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal  
at the X1 input, and following any changes to the SELn inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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