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CDC960DLG4 PDF预览

CDC960DLG4

更新时间： 2024-11-17 14:41:23
品牌 Logo 应用领域
德州仪器 - TI 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
37页 532K
描述
200-MHz Clock Synthesizer/Driver with Spread Spectrum & Device Control Interface 48-SSOP 0 to 70

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中文翻译

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CDC960DLG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SO-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.8Is Samacsys：N
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：15.875 mm湿度敏感等级：2
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：200 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V主时钟/晶体标称频率：16 MHz
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Clock Generators最大压摆率：185 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CDC960DLG4 数据手册

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SCAS675 – APRIL 2002  
DL PACKAGE  
(TOP VIEW)  
D
D
D
Generates Clocks for AMD-K8 Clawhammer  
Desktop Systems  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
FS0 & REF0  
FS1 & REF1  
GND  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
2
3
4
5
6
7
8
9
DD  
Includes Spread Spectrum Clocking (SSC),  
0.5% Downspread for Reduced EMI  
XIN  
XOUT  
GND  
V
DD  
FS2 & REF2  
SPREAD  
D
Power Management Control Terminals  
D
SMBus Serial Interface Provides Output  
Enable and Control  
PCI/LDT_SEL  
PCI/LDT0  
V
DDA  
GNDA  
CPU0  
CPU0  
GND  
PCI/LDT1  
D
Low-Output Skew and Low Jitter for Clock  
Distribution  
V
DD  
GND  
PCI/LDT2  
LDT_Stop  
PCI0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
Operates From Single 3.3-V Supply  
V
DD  
D
Generates the Following Clocks:  
– 2 CPU (3.3 V, 180° shifted pairs,  
200/166/133/100 MHz)  
CPU1  
CPU1  
PCI1  
V
DD  
– 6 PCI (3.3 V, 33 MHz)  
GND  
GND  
– 1 PCI_F (3.3 V, 33 MHz)  
– 3 REF (3.3 V, 14.318 MHz)  
– 1 USB (3.3 V, 48 MHz)  
V
GNDF  
DD  
PCI2  
PCI3  
V
DDF  
USB  
GND  
– 1 FDC (3.3 V, 24 MHz or 48 MHz)  
V
†
DD  
– 3 PCI/LDT (3.3 V, 33 MHz or 66 MHz)  
GND  
PCI4  
V
DD  
D
Packaged in 48-Pin SSOP Package  
24/48_SEL & FDC  
GND  
PCI5  
description  
PCI_F  
SDATA  
The CDC960 is a clock synthesizer/driver and  
PCI_Stop  
SCLK  
buffer that generates CPU, PCI, PCI/LDT, USB,  
FDC, and REF system clock signals to support  
PCs with an AMD-K8 Clawhammer-class system.  
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided  
at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this  
case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.  
On-chip loop filters and internal feedback eliminate the need for external components.  
The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The  
implementation is as a slave with read and write capability. The device address is specified in the SMBus serial  
interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors  
(typically 150 kΩ).  
Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs  
default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level  
control bit is written to the control register. The registers must be accessed in sequential order (i.e., random  
access of the registers not supported).  
The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter  
clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control  
inputs FS0, FS1, and FS2 at power-up preset condition.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
LDT is equivalent to HT66 shown on AMD specification.  
Copyright 2002, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...37

中文翻译

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CDC960DLG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC960DLR TI

完全替代

 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF

与CDC960DLG4相关器件

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CDC960DLR TI

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 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC9841 TI

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 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS
CDC9841DW TI

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 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS
CDC9841DWR TI

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CDC9842 TI

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 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
CDC9842DW ROCHESTER

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 		Processor Specific Clock Generator, 66MHz, BICMOS, PDSO28, PLASTIC, SOIC-28
CDC9842DW TI

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 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
CDC9842DWR TI

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 		3.3Vdriver 28-SOIC
CDC9842DWR ROCHESTER

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 		66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28, PLASTIC, SOIC-28
CDC9843 TI

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 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

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