Datasheet > CDCD5704_07

CDCD5704_07

更新时间： 2024-01-13 17:54:12

品牌	Logo	应用领域
德州仪器 - TI		时钟发生器
页数	文件大小	规格书
19页	310K
描述
Rambus XDR CLOCK GENERATOR

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中文翻译

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数据手册

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CDCD5704_07 数据手册

CDCD5704

www.ti.com

SCAS823–DECEMBER 2006

Rambus™ XDR™ CLOCK GENERATOR

FEATURES

PW PACKAGE

(TOP VIEW)

•

High-Speed Clock Support: 300-MHz–667-MHz

Clock Source for XDR Memory Subsystems

and Redwood Logic Interface

VDDP

VSSP

ISET

VDD

CLK0

CLK0B

VSS

•

Quad (Open-Drain) Differential Output Drivers

Spread-Spectrum Compatible Clock Input Can

Be Distributed to Minimize EMI

VSS

REFCLK

REFCLKB

VDDC

VSSC

SCL

CLK1

CLK1B

•

Differential or Single-Ended Reference Clock

Input of 100 MHz or 133 MHz

VDD

VSS

Serial Interface Features: Programmable

Frequency Multiplier, Select Any One to Four

Outputs and Mode of Operation

CLK2

CLK2B

SDA

VSS

•

Supports Frequency Multiplication Factors of:

×3, ×4, ×5, ×6, ×8, ×9/2, ×15/2, ×15/4

ID0

CLK3

CLK3B

VDD

ID1

BYPASS

All PLL Loop Filter Components Are

Integrated

P0043-01

Low |Cycle-to-Cycle| of 1–6 Cycle Jitter:

–

40 ps: 300–635 MHz

30 ps: 636–667 MHz

•

PLLs Are Powered Down if No Valid REF

Clock (<10 MHz) Is Detected or VDD Is Below

1.6 V

•

Operates From Single 2.5-V Supply (±0.125 V)

Packaged in TSSOP-28

Commercial Temperature Range 0°C to 70°C

APPLICATIONS

•

XDR Memory Subsystem and Redwood Logic

Interface

DESCRIPTION

The CDCD5704 clock generator provides the necessary clock signals to support an XDR memory subsystem

and Redwood logic interface using a reference clock input with or without spread-spectrum modulation.

Contained in a 28-pin TSSOP package that includes four differential clock outputs, the CDCD5704 provides an

off-the-shelf solution for a broad range of high-performance interface applications.

The block diagram shows the major components of the CDCD5704, which include a phase-locked loop, a

bypass multiplexer, and four differential output buffers (CLK0 to CLK3). All four outputs can be disabled by a

logical low at the input of the EN pin. An output is enabled when EN is high and a value of 1 is in its serial

interface register (RegA–RegD).

The PLL receives a reference clock input signal, REFCLK, and outputs a clock signal at a frequency equal to the

input frequency times the multiplication factor. The PLL output clock signal is fed to the differential output buffers

to drive the enabled clocks. Disabled outputs are set to high impedance.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Rambus, XDR are trademarks of Rambus Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...19

中文翻译

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与CDCD5704_07相关器件

型号	品牌	获取价格	描述	数据表
CDCD5704PW	TI	获取价格	Rambus TM XDR TM CLOCK GENERATOR
CDCD5704PWG4	TI	获取价格	Rambus TM XDR TM CLOCK GENERATOR
CDCD5704PWR	TI	获取价格	Rambus TM XDR TM CLOCK GENERATOR
CDCD5704PWRG4	TI	获取价格	Rambus TM XDR TM CLOCK GENERATOR
CDCDB2000	TI	获取价格	符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20
CDCDB2000NPPR	TI	获取价格	符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20
CDCDB2000NPPT	TI	获取价格	符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20
CDCDB400	TI	获取价格	适用于 PCIe® 第 1 代到第 5 代的 4 路输出时钟缓冲器
CDCDB400RHBR	TI	获取价格	适用于 PCIe® 第 1 代到第 5 代的 4 路输出时钟缓冲器 \| RHB \| 32
CDCDB400RHBT	TI	获取价格	适用于 PCIe® 第 1 代到第 5 代的 4 路输出时钟缓冲器 \| RHB \| 32

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