CDCE18005
www.ti.com........................................................................................................................................................................................... SCAS863–NOVEMBER 2008
Five/Ten Output Clock Generator/Buffer
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FEATURES
APPLICATIONS
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Data Converter and Data Aggregation Clocking
Wireless Infrastructure
Switches and Routers
Medical Electronics
Military and Aerospace
Industrial
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Universal Input Buffers That Accept LVPECL,
LVDS, or LVCMOS Level Signaling
Fully Configurable Outputs Including
Frequency, Output Format, and Output Skew
Output Multiplexer That Serves as a Clock
Switch Between the Three Reference Inputs
and the Outputs
Clock Fan-out
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Clock Generation Via AT-Cut Crystal
DESCRIPTION
Integrated EEPROM Determines Device
Configuration at Power-up
The CDCE18005 is
a high performance clock
generator and distributor featuring a high degree of
configurability via a SPI interface, and programmable
start up modes determined by on-board EEPROM.
Specifically tailored for buffering clocks for data
converters and high-speed digital signals, the
CDCE18005 achieves low additive jitter in the 50 fs
RMS(1) range. The clock distribution block includes
five individually programmable outputs that can be
configured to provide different combinations of output
formats (LVPECL, LVDS, LVCMOS). Each output can
also be programmed to a unique output frequency
(up to 1.5 GHz(2) ) and skew relationship via a
programmable delay block. If all outputs are
configured in single-ended mode (e.g. LVCMOS), the
CDCE18005 supports up to ten outputs. Each output
can select one of three clock input sources. The input
block includes two universal differential inputs which
support frequencies up to 1500 MHz and an auxiliary
single ended input that can be connected to a CMOS
level clock or configured to connect to an external
crystal via an on board oscillator block.
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Low Additive Jitter Performance
Universal Output Blocks Support up to 5
Differential, 10 Single-ended, or Combinations
of Differential or Single-ended:
– Low Additive Jitter
– Output Frequency up to 1.5 GHz
– LVPECL, LVDS, LVCMOS, and Special High
Output Swing Modes
– Independent Output Dividers Support
Divide Ratios from 1–80
– Independent limited Coarse Skew Control
on all Outputs
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Flexible Inputs:
– Two Universal Differential Inputs Accept
Frequencies up to 1500 MHz (LVPECL), 800
MHz (LVDS), or 250 MHz (LVCMOS).
– One Auxiliary Input Accepts Single Ended
Clock Source or Crystal. Auxiliary Input
Accepts Crystals in the Range of 2 MHz–42
MHz or an LVCMOS Input up to 75 MHz.
LVCMOS 25MHz
LVPECL 1.5GHz / LVDS 800MHz
LVCMOS 25MHz
LVPECL 800MHz
LVDS 750MHz
– Clock Generator Mode Using Crystal Input.
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Typical Power Consumption 1.0W at 3.3V (see
Table 27)
CDCE18005
LVDS 800MHz
Crystal 25MHz
Integrated EEPROM Stores Default Settings;
Therefore, The Device Powers up in a Known,
Predefined State.
LVPECL 1.5GHz
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Offered in QFN-48 Package
Figure 1. CDCE18005 Application Example
ESD Protection Exceeds 2kV HBM
Industrial Temperature Range –40°C to 85°C
(1) 12 kHz to 20 MHz integration bandwidth.
(2) Maximum output frequency depends on the output format
selected
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated