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CDCE6214RGER PDF预览

CDCE6214RGER

更新时间: 2023-09-03 20:35:56
品牌 Logo 应用领域
德州仪器 - TI 时钟时钟发生器
页数 文件大小 规格书
55页 5707K
描述
具有一个 PLL、四个差分输出的超低功耗时钟发生器 | RGE | 24 | -40 to 105

CDCE6214RGER 数据手册

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CDCE6214  
SNAS811 JULY 2020  
CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs,  
Two Inputs, and Internal EEPROM  
1 Features  
Integrated EEPROM with two pages and  
external select pin. In-situ programming  
allowed.  
1
Configurable high performance, low-power, frac-N  
PLL with RMS jitter with spurs (12 kHz – 20 MHz,  
Fout > 100 MHz) as:  
Supports 100-Ω systems  
Low electromagnetic emissions  
Small footprint: 24-pin VQFN (4 mm × 4 mm)  
Integer mode:  
Differential output: 350 fs typical, 600 fs  
maximum  
2 Applications  
LVCMOS output: 1.05 ps typical, 1.5 ps  
maximum  
PCIe Gen 1 - Gen 5 clocking  
Data Center & Enterprise Computing, PC &  
Notebook  
Fractional mode:  
Differential output: 1.7 ps typical, 2.1 ps  
maximum  
Enterprise Machine - Multi-Function Printer  
Test & Measurement, Handheld Equipment  
LVCMOS output: 2.0 ps typical, 4.0 ps  
maximum  
3 Description  
Supports PCIe Gen1/2/3/4 with SSC and Gen  
1/2/3/4/5 without SSC  
The CDCE6214 is a four-channel, ultra-low power,  
medium grade jitter, clock generator that can  
generate five independent clock outputs selectable  
between various modes of drivers. The input source  
could be a single-ended or differential input clock  
source, or a crystal. The CDCE6214 features a frac-N  
PLL to synthesize unrelated base frequency from any  
input frequency. The CDCE6214 can be configured  
through the I2C interface. In the absence of the serial  
interface, the GPIO pins can be used in Pin Mode to  
configure the product into distinctive configurations.  
2.335-GHz to 2.625-GHz internal VCO  
Typical power consumption: 65 mA for 4-output  
channel, 23 mA for 1-output channel.  
Universal clock input, two reference inputs for  
redundancy  
Differential AC-coupled or LVCMOS: 10 MHz  
to 200 MHz  
Crystal: 10 MHz to 50 MHz  
Flexible output clock distribution  
Device Information(1)  
4 channel dividers: Up to 5 unique output  
frequencies from 24 kHz to 328.125 MHz  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
CDCE6214  
VQFN (24)  
4.00 mm × 4.00 mm  
Combination of LVDS-like, LP-HCSL or  
LVCMOS outputs on OUT0 – OUT4 pins  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Glitchless output divider switching and output  
channel synchronization  
Application Example CDCE6214  
Individual output enable through GPIO and  
register  
Voltage Domain  
1.8V / 2.5V / 3.3V  
FPGA  
Frequency margining options  
DCO mode: frequency increment/decrement  
with 10ppb or less step-size  
Crystal  
DAC  
Voltage Domain  
1.8V / 2.5V / 3.3V  
CDCE6214  
Fully-integrated, configurable loop bandwidth: 100  
kHz to 1.6 MHz  
MCU  
Single or mixed supply for level translation: 1.8  
V/2.5 V/3.3 V  
Ethernet  
LVCMOS  
Crystal Copy  
PCIe  
Voltage Domain  
1.8V / 2.5V / 3.3V  
Configurable GPIOs and flexible configuration  
options  
I2C-compatible interface: up to 400 kHz  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 

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