CDCE906
www.ti.com
SCAS814H–NOVEMBER 2005–REVISED DECEMBER 2007
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
1
FEATURES
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Programmable Down Spread SSC Modulation
(1%, 1.5%, 2%, and 3%)
2
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High Performance 3:6 PLL based Clock
Synthesizer / Multiplier / Divider
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Programmable Output Slew-Rate Control
(SRC) for Lowering System EMI
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User Programmable PLL Frequencies
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3.3-V Device Power Supply
EEPROM Programming Without the Need to
Apply High Programming Voltage
Commercial Temperature Range 0°C to 70°C
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Easy In-Circuit Programming via SMBus Data
Interface
Development and Programming Kit for Easy
PLL Design and Programming
(TI Pro-Clock™)
Wide PLL Divider Ratio Allows 0-ppm Output
Clock Error
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Packaged in 20-Pin TSSOP
Generates Precise Video (27 MHz or 54 MHz)
and Audio System Clocks from Multiple
Sampling Frequencies (fS = 16, 22.05, 24, 32,
44.1, 48, 96 kHz)
TERMINAL ASSIGNMENT
PW PACKAGE
(TOP VIEW)
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Clock Inputs Accept a Crystal or a
Single-Ended LVCMOS or a Differential Input
Signal
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0/A0/CLK_SEL
Y5
Y4
VCCOUT2
GND
Y3
S1/A1
VCC
GND
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Accepts Crystal Frequencies from 8 MHz up to
54 MHz
TSSOP 20
Pitch 0,65 mm
6.6 x 6.6
CLK_IN0
CLK_IN1
VCC
GND
SDATA
SCLOCK
Accepts LVCMOS or Differential Input
Frequencies up to 167 MHz
Y2
VCCOUT1
GND
Y1
Two Programmable Control Inputs [S0/S1,
A0/A1] for User Defined Control Signals
Y0
Six LVCMOS Outputs with Output Frequencies
up to 167 MHz
LVCMOS Outputs can be Programmed for
Complementary Signals
DESCRIPTION
The CDCE906 is one of the smallest and powerful
PLL synthesizer / multiplier / divider available today.
Despite its small physical outlines, the CDCE906 is
flexible. It has the capability to produce an almost
independent output frequency from a given input
frequency.
Free Selectable Output Frequency via
Programmable Output Switching Matrix [6x6]
Including 7-Bit Post-Divider for Each Output
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PLL Loop Filter Components Integrated
Low Period Jitter (Typ 60 ps)
The input frequency can be derived from a LVCMOS,
differential input clock, or a single crystal. The
appropriate input waveform can be selected via the
SMBus data interface controller.
Features Spread Spectrum Clocking (SSC) for
Lowering System EMI
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Programmable Center Spread SSC Modulation
(±0.1%, ±0.25%, and ±0.4%) with a Mean Phase
Equal to the Phase of the Non-Modulated
Frequency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Pro-Clock is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated