Datasheet > 逻辑 > 时钟驱动器> CDCE72010RGCTG4

CDCE72010RGCTG4

更新时间： 2024-01-30 03:05:32

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器逻辑集成电路
页数	文件大小	规格书
73页	1782K
描述
Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

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CDCE72010RGCTG4 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	VQFN-64	针数：	64
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks	风险等级：	5.23
Is Samacsys：	N	系列：	72010
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQCC-N64
JESD-609代码：	e4	长度：	9 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	64	实输出次数：	10
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	包装方法：	TR
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	3.4 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	2.8 ns
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	9 mm
最小 fmax：	1500 MHz	Base Number Matches：	1

CDCE72010RGCTG4 数据手册

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A–JUNE 2008–REVISED JULY 2009

Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

FEATURES

•

Wide Charge-Pump Current Range From

200µA to 3mA

•

High Performance LVPECL, LVDS, LVCMOS

PLL Clock Synchronizer

Dedicated Charge-Pump Supply for Wide

Tuning Voltage Range VCOs

•

Two Reference Clock Inputs (Primary and

Secondary Clock) for Redundancy Support

with Manual or Automatic Selection

Presets Charge-Pump to V_{CC_CP}/2 for Fast

Center-Frequency Setting of VC(X)O,

Controlled Via the SPI Bus

•

Accepts Two Differential Input (LVPECL or

LVDS) References up to 500MHz (or Two

LVCMOS Inputs up to 250MHz) as PLL

Reference

•

SERDES Startup Mode (Depending on VCXO

Range)

Auxiliary Input: Output 9 can Serve as 2nd

VCXO Input to Drive All Outputs or to Serve as

PLL Feedback Signal

•

VCXO_IN Clock is Synchronized to One of Two

Reference Clocks

VCXO_IN Frequencies up to 1.5GHz (LVPECL)

800Mhz for LVDS and 250MHz for LVCMOS

Level Signaling

•

RESET or HOLD Input Pin to Serve as Reset or

Hold Functions

REFERENCE SELECT for Manual Select

Between Primary and Secondary Reference

Clocks

•

Outputs Can be a Combination of LVPECL,

LVDS, and LVCMOS (Up to 10 Differential

LVPECL or LVDS Outputs or up to 20 LVCMOS

Outputs), Output 9 can be Converted to an

Auxiliary Input as a 2nd VC(X)O.

•

POWER DOWN (PD) to Put Device in Standby

Mode

•

Analog and Digital PLL Lock Indicator

Output Divider is Selectable to Divide by 1, 2,

3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,

40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each

Output Individually up to Eight Dividers.

(Except for Output 0 and 9, Output 0 Follows

Output 1 Divider and Output 9 Follows Output

8 Divider)

Internally Generated VBB Bias Voltages for

Single-Ended Input Signals

•

Frequency Hold-Over Mode Activated by

HOLD Pin or SPI Bus to Improve Fail-Safe

Operation

•

Input to All Outputs Skew Control

Individual Skew Control for Each Output with

Each Output Divider

•

SPI Controllable Device Setting

Individual Output Enable Control via SPI

Interface

•

Packaged in a QFN-64 Package

ESD Protection Exceeds 2kV HBM

Industrial Temperature Range of –40°C to 85°

•

Integrated On-Chip Non-Volatile Memory

(EEPROM) to Store Settings without the Need

to Apply High Voltage to the Device

APPLICATIONS

•

Optional Configuration Pins to Select Between

Two Default Settings Stored in EEPROM

•

Low Jitter Clock Driver for High-End Telecom

and Wireless Applications

Efficient Jitter Cleaning from Low PLL Loop

Bandwidth

•

High Precision Test Equipment

•

Very Low Phase Noise PLL Core

Programmable Phase Offset (Input Reference

to Outputs)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...73

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CDCE72010RGCTG4 替代型号

型号	品牌	替代类型	描述	数据表
CDCE72010RGCRG4	TI	完全替代	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010RGCR	TI	完全替代	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010RGCT	TI	类似代替	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

与CDCE72010RGCTG4相关器件

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CDCE913	TI	获取价格	Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs

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