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CDCE906 PDF预览

CDCE906

更新时间: 2024-11-20 23:14:31
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
33页 1644K
描述
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

CDCE906 数据手册

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CDCE906  
www.ti.com  
SCAS814NOVEMBER 2005  
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER  
FEATURES  
Programmable Down Spread SSC Modulation  
(1%, 1.5%, 2%, and 3%)  
High Performance 2:6 PLL based Clock  
Synthesizer / Multiplier / Divider  
Programmable Output Slew-Rate Control  
(SRC) for Lowering System EMI  
User Programmable PLL Frequencies using  
EEPROM Technology  
Separate Power Supplies for Outputs (2.3 V to  
3.6 V) Supports Mixed Power Supply  
Environments  
EEPROM Programming Without the Need to  
Apply High Programming Voltage  
3.3-V Device Power Supply  
Easy In-Circuit Programming via SMBus Data  
Interface  
Industrial Temperature Range 0°C to 70°C  
Wide PLL Divider Ratio Allows 0-ppm Output  
Clock Error  
Development and Programming Kit for Ease  
PLL Design and Programming (TI  
Pro-Clock™)  
Generates Precise Video (27 or 54 MHz) and  
Audio System Clocks from Multiple Sampling  
Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96  
kHz)  
Packaged in 20-Pin TSSOP  
TERMINAL ASSIGNMENT  
Clock Inputs Accept a Crystal or a  
Single-Ended LVCMOS or a Differential Input  
Signal  
PW PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0/A0/CLK_SEL  
S1/A1  
Y5  
Y4  
V
CCOUT2  
Accepts Crystal Frequencies from 8 MHz up  
to 54 MHz  
V
CC  
Accepts LVCMOS or Differential Input  
Frequencies up to 167 MHz  
GND  
CLK_IN0  
CLK_IN1  
GND  
Y3  
Y2  
V
TSSOP 20  
Pitch 0,65 mm  
6.6 x 6.6  
Two Programmable Control Inputs [S0/S1,  
A0/A1] for User Defined Control Signals  
V
CC  
CCOUT1  
GND  
SDATA  
SCLOCK  
GND  
Y1  
Y0  
Six LVCMOS Outputs with Output  
Frequencies up to 167 MHz  
LVCMOS Outputs can be Programmed for  
Complementary Signals (Pseudo Differential  
Outputs)  
Free Selectable Output Frequency via  
Programmable Output Switching Matrix [6x6]  
Including 7-Bit Post-Divider for Each Output  
PLL Loop Filter Components Integrated  
Low Period Jitter (Typ 60 ps)  
Features Spread Spectrum Clocking (SSC) for  
Lowering System EMI  
Programmable Center Spread SSC Modulation  
(±0.1%, ±0.25%, and ±0.4%) with a Mean Phase  
Equal to the Phase of the Non-Modulated  
Frequency  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Pro-Clock is a trademark of Texas Instruments.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2005, Texas Instruments Incorporated  

CDCE906 替代型号

型号 品牌 替代类型 描述 数据表
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