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CDCE706

更新时间： 2024-02-06 19:10:06
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
32页 1632K
描述
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

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中文翻译

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CDCE706 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.04Is Samacsys：N
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm湿度敏感等级：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：300 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260主时钟/晶体标称频率：200 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
最大压摆率：115 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, VIDEO
Base Number Matches：1

CDCE706 数据手册

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CDCE706  
www.ti.com  
SCAS815A–OCTOBER 2005–REVISED OCTOBER 2005  
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER  
FEATURES  
•
Separate Power Supplies for Outputs (2.3 V to  
3.6 V) Supports Mixed Power Supply  
Environments  
•
•
•
•
•
•
High Performance 2:6 PLL based Clock  
Synthesizer / Multiplier / Divider  
•
•
•
3.3-V Device Power Supply  
User Programmable PLL Frequencies using  
EEPROM Technology  
Industrial Temperature Range –40°C to 85°C  
EEPROM Programming Without the Need to  
Apply High Programming Voltage  
Development and Programming Kit for Ease  
PLL Design and Programming (TI  
Pro-Clock™)  
Easy In-Circuit Programming via SMBus Data  
Interface  
•
Packaged in 20-Pin TSSOP  
Wide PLL Divider Ratio Allows 0-ppm Output  
Clock Error  
TERMINAL ASSIGNMENT  
Clock Inputs Accept a Crystal or a  
Single-Ended LVCMOS or a Differential Input  
Signal  
PW PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
S0/A0/CLK_SEL  
S1/A1  
Y5  
Y4  
V
CCOUT2  
GND  
Y3  
Y2  
V
CCOUT1  
GND  
Y1  
•
•
•
•
•
Accepts Crystal Frequencies from 8 MHz up  
to 54 MHz  
V
CC  
Accepts LVCMOS or Differential Input  
Frequencies up to 200 MHz  
GND  
CLK_IN0  
CLK_IN1  
TSSOP 20  
Pitch 0,65 mm  
6.6 x 6.6  
Two Programmable Control Inputs [S0/S1,  
A0/A1] for User Defined Control Signals  
V
CC  
GND  
SDATA  
SCLOCK  
Six LVCMOS Outputs with Output  
Frequencies up to 300 MHz  
Y0  
LVCMOS Outputs can be Programmed for  
Complementary Signals (Pseudo Differential  
Outputs)  
•
Free Selectable Output Frequency via  
Programmable Output Switching Matrix [6x6]  
Including 7-Bit Post-Divider for Each Output  
•
•
•
PLL Loop Filter Components Integrated  
Low Period Jitter (Typ 60 ps)  
Features Spread Spectrum Clocking (SSC) for  
Lowering System EMI  
•
Programmable Output Slew-Rate Control  
(SRC) for Lowering System EMI  
DESCRIPTION  
The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite  
its small physical outlines, the CDCE706 is the most flexible. It has the capability to produce an almost  
independent output frequency from a given input frequency.  
The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate  
input waveform can be selected via the SMBus data interface controller.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Pro-Clock is a trademark of Texas Instruments.  
PRODUCT PREVIEW information concerns products in the  
Copyright © 2005, Texas Instruments Incorporated  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
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中文翻译

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CDCE706 替代型号

型号 品牌 替代类型 描述 数据表
CDC706 TI

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