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CDCE706_10 PDF预览

CDCE706_10

更新时间: 2024-01-07 16:27:33
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德州仪器 - TI 时钟
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40页 1007K
描述
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER

CDCE706_10 数据手册

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CDCE706  
www.ti.com ........................................................................................................................................... SCAS815IOCTOBER 2005REVISED NOVEMBER 2008  
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER  
1
FEATURES  
TERMINAL ASSIGNMENT  
High-Performance 3:6 PLL-Based Clock  
Synthesizer/Multiplier/Divider  
PW Package  
(Top View)  
User-Programmable PLL Frequencies  
EEPROM Programming Without the Need to  
Apply High Programming Voltage  
S0/A0/CLK_SEL  
S1/A1  
1
2
3
4
5
6
7
8
9
10  
Y5  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Y4  
Easy In-Circuit Programming via SMBus Data  
Interface  
VCC  
VCCOUT2  
GND  
GND  
Y3  
CLK_IN0  
Wide PLL Divider Ratio Allows 0-ppm Output  
Clock Error  
CLK_IN1  
VCC  
Y2  
VCCOUT1  
Clock Inputs Accept a Crystal, a Single-Ended  
LVCMOS, or a Differential Input Signal  
GND  
GND  
Y1  
SDATA  
SCLOCK  
Accepts Crystal Frequencies From 8 MHz to  
54 MHz  
Y0  
P0087-01  
Accepts LVCMOS or Differential Input  
Frequencies up to 200 MHz  
DESCRIPTION  
Two Programmable Control Inputs [S0/S1,  
A0/A1] for User-Defined Control Signals  
The CDCE706 is one of the smallest and most  
powerful PLL synthesizer/multiplier/dividers available  
today. Despite its small physical outline, the  
CDCE706 is very flexible. It has the capability to  
produce an almost independent output frequency  
from a given input frequency.  
Six LVCMOS Outputs With Output Frequencies  
up to 300 MHz  
LVCMOS Outputs Can Be Programmed for  
Complementary Signals  
Free Selectable Output Frequency via  
Programmable Output Switching Matrix [6×6]  
Including 7-Bit Post-Divider for Each Output  
The input frequency can be derived from an  
LVCMOS, differential input clock, or single crystal.  
The appropriate input waveform can be selected via  
the SMBus data interface controller.  
PLL Loop Filter Components Integrated  
Low Period Jitter (Typically 60 ps)  
To achieve an independent output frequency, the  
reference divider M and the feedback divider N for  
each PLL can be set to values from 1 to 511 for the  
M-divider and from 1 to 4095 for the N-divider. The  
PLL-VCO (voltage controlled oscillator) frequency  
then is routed from the programmable output  
switching matrix to any of the six outputs. The  
switching matrix includes an additional 7-bit  
post-divider (1 to 127) and an inverting logic for each  
output.  
Features Spread-Spectrum Clocking (SSC) for  
Lowering System EMI  
Programmable Output Slew-Rate Control  
(SRC) for Lowering System EMI  
3.3-V Device Power Supply  
Industrial Temperature Range –40°C to 85°C  
Development and Programming Kit for Easy  
PLL Design and Programming (TI ClockPro  
Software)  
The deep M/N divider ratio allows the generation of  
zero-ppm clocks from any reference input frequency  
(e.g., 27 MHz).  
Packaged in 20-Pin TSSOP  
The CDCE706 includes three PLLs; of those, one  
supports spread-spectrum clocking (SSC). PLL1,  
PLL2, and PLL3 are designed for frequencies up to  
300 MHz and optimized for zero-ppm applications  
with wide divider factors.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2008, Texas Instruments Incorporated  

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