Datasheet > CDCE72010_09

CDCE72010_09

更新时间： 2024-11-21 11:51:31

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
73页	1782K
描述
Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

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CDCE72010_09 数据手册

CDCE72010

www.ti.com.............................................................................................................................................................. SCAS858A–JUNE 2008–REVISED JULY 2009

Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

FEATURES

•

Wide Charge-Pump Current Range From

200µA to 3mA

•

High Performance LVPECL, LVDS, LVCMOS

PLL Clock Synchronizer

Dedicated Charge-Pump Supply for Wide

Tuning Voltage Range VCOs

•

Two Reference Clock Inputs (Primary and

Secondary Clock) for Redundancy Support

with Manual or Automatic Selection

Presets Charge-Pump to V_{CC_CP}/2 for Fast

Center-Frequency Setting of VC(X)O,

Controlled Via the SPI Bus

•

Accepts Two Differential Input (LVPECL or

LVDS) References up to 500MHz (or Two

LVCMOS Inputs up to 250MHz) as PLL

Reference

•

SERDES Startup Mode (Depending on VCXO

Range)

Auxiliary Input: Output 9 can Serve as 2nd

VCXO Input to Drive All Outputs or to Serve as

PLL Feedback Signal

•

VCXO_IN Clock is Synchronized to One of Two

Reference Clocks

VCXO_IN Frequencies up to 1.5GHz (LVPECL)

800Mhz for LVDS and 250MHz for LVCMOS

Level Signaling

•

RESET or HOLD Input Pin to Serve as Reset or

Hold Functions

REFERENCE SELECT for Manual Select

Between Primary and Secondary Reference

Clocks

•

Outputs Can be a Combination of LVPECL,

LVDS, and LVCMOS (Up to 10 Differential

LVPECL or LVDS Outputs or up to 20 LVCMOS

Outputs), Output 9 can be Converted to an

Auxiliary Input as a 2nd VC(X)O.

•

POWER DOWN (PD) to Put Device in Standby

Mode

•

Analog and Digital PLL Lock Indicator

Output Divider is Selectable to Divide by 1, 2,

3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,

40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each

Output Individually up to Eight Dividers.

(Except for Output 0 and 9, Output 0 Follows

Output 1 Divider and Output 9 Follows Output

8 Divider)

Internally Generated VBB Bias Voltages for

Single-Ended Input Signals

•

Frequency Hold-Over Mode Activated by

HOLD Pin or SPI Bus to Improve Fail-Safe

Operation

•

Input to All Outputs Skew Control

Individual Skew Control for Each Output with

Each Output Divider

•

SPI Controllable Device Setting

Individual Output Enable Control via SPI

Interface

•

Packaged in a QFN-64 Package

ESD Protection Exceeds 2kV HBM

Industrial Temperature Range of –40°C to 85°

•

Integrated On-Chip Non-Volatile Memory

(EEPROM) to Store Settings without the Need

to Apply High Voltage to the Device

APPLICATIONS

•

Optional Configuration Pins to Select Between

Two Default Settings Stored in EEPROM

•

Low Jitter Clock Driver for High-End Telecom

and Wireless Applications

Efficient Jitter Cleaning from Low PLL Loop

Bandwidth

•

High Precision Test Equipment

•

Very Low Phase Noise PLL Core

Programmable Phase Offset (Input Reference

to Outputs)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...73

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与CDCE72010_09相关器件

型号	品牌	获取价格	描述	数据表
CDCE72010RGCR	TI	获取价格	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010RGCRG4	TI	获取价格	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010RGCT	TI	获取价格	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE72010RGCTG4	TI	获取价格	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
CDCE813-Q1	TI	获取价格	具有 2.5V 和 3.3V 输出的可编程 1-PLL 时钟合成器和抖动消除器
CDCE813QPWRQ1	TI	获取价格	具有 2.5V 和 3.3V 输出的可编程 1-PLL 时钟合成器和抖动消除器 \| PW
CDCE813R02TPWRQ1	TI	获取价格	具有 2.5V 和 3.3V 输出的可编程 1-PLL 时钟合成器和抖动消除器 \| PW
CDCE906	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE906_10	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE906PW	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER

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