CDCDLP223

更新时间： 2024-11-30 04:11:43

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
7页	148K
描述
3.3 V Clock Synthesizer for DLP TM Systems

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CDCDLP223 数据手册

CDCDLP223

www.ti.com

SCAS836–DECEMBER 2006

3.3 V Clock Synthesizer for DLP™ Systems

FEATURES

CDCDLP223 PIN ASSIGNMENTS

•

High-Performance Clock Synthesizer

•

Uses a 20 MHz Crystal Input to Generate

Multiple Output Frequencies

TSSOP 20

XIN

XOUT

VSS

IREF

VDD

•

Integrated Load Capacitance for 20 MHz

Oscillator Reducing System Cost

100MHZ

VSS

All PLL Loop Filter Components are

Integrated

VDD

20MHZ

VSS

Generates the Following Clocks:

VSS

–

REF CLK 20 MHz (Buffered)

XCG CLK 100 MHz With SSC

300MHZ

VSS

IDO

DMD CLK 200-400 MHz With Selectable

SSC

SDATA

SCLK

•

Very Low Period Jitter Characteristic:

VDD

–

±100 ps at 20 MHz Output

±75 ps at 100 MHz and 200–400 MHz

Outputs

The 100 MHz HCLK output provides the reference

clock for the XDR Clock Generator (CDCD5704).

Spread-spectrum clocking with 0.5% down spread,

which reduces Electro Magnetic Interference (EMI),

is applied in the default configuration. The

spread-spectrum clocking (SSC) is turned on and off

via the serial control interface.

•

Includes Spread-Spectrum Clocking (SSC),

With Down Spread for 100 MHz and Center

Spread for 200–400 MHz

HCLK Differential Outputs for the 100 MHz

and the 200–400 MHz Clock

•

Operates From Single 3.3-V Supply

Packaged in TSSOP20

The 300 MHz HCLK output provides a 200-400 MHz

clock signal for the DMD Control Logic of the DLP™

Control ASIC. Frequency selection in 20 MHz steps

is possible via the serial control interface.

Spread-spectrum clocking with ±1.0% or ±1.5%

center spread is applied, which can be disabled via

the serial control interface

Characterized for the Industrial Temperature

Range -40°C to 85°C

•

ESD Protection Exceeds JESD22

2000-V Human-Body Model (A114-C) –

MIL-STD-883, Method 3015

The CDCDLP223 features a fail safe start-up circuit,

which enables the PLLs only if a sufficient supply

voltage is applied and a stable oscillation is delivered

from the crystal oscillator. After the crystal start-up

time and the PLL stabilization time, all outputs are

ready for use.

TYPICAL APPLICATIONS

•

Central Clock Generator for DLP™ Systems

DESCRIPTION

The CDCDLP223 is a PLL-based high performance

clock synthesizer that is optimized for use in DLP™

systems. It uses a 20 MHz crystal to generate the

fundamental frequency and derives the frequencies

for the 100 MHz HCLK and the 300 MHz HCLK

The CDCDLP223 works from a single 3.3-V supply

and is characterized for operation from –40°C to

85°C.

output. Further, the CDCDLP223 generates

buffered copy of the 20 MHz Crystal Oscillator

Frequency at the 20 MHz output terminal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7

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与CDCDLP223相关器件

型号	品牌	获取价格	描述	数据表
CDCDLP223_07	TI	获取价格	3.3 V Clock Synthesizer for DLP Systems
CDCDLP223PW	TI	获取价格	用于 DLP 系统的 3.3V 时钟合成器 \| PW \| 20 \| -40 to 85
CDCDLP223PWR	TI	获取价格	3.3 V Clock Synthesizer for DLP Systems
CDCE18005	TI	获取价格	Five/Ten Output Clock Generator/Buffer
CDCE18005RGZR	TI	获取价格	Five/Ten Output Clock Generator/Buffer
CDCE18005RGZT	TI	获取价格	Five/Ten Output Clock Generator/Buffer
CDCE401	TI	获取价格	OSCILLATOR IC WITH ELECTRONIC CALIBRATION
CDCE401YS	TI	获取价格	OSCILLATOR IC WITH ELECTRONIC CALIBRATION
CDCE421	TI	获取价格	Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator
CDCE421_15	TI	获取价格	Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator

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