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CDC9843

更新时间： 2024-11-16 21:53:35
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件PC时钟
页数 文件大小 规格书
8页 123K
描述
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

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CDC9843 数据手册

 浏览型号CDC9843的Datasheet PDF文件第2页浏览型号CDC9843的Datasheet PDF文件第3页浏览型号CDC9843的Datasheet PDF文件第4页浏览型号CDC9843的Datasheet PDF文件第5页浏览型号CDC9843的Datasheet PDF文件第6页浏览型号CDC9843的Datasheet PDF文件第7页 
CDC9843  
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS559C – DECEMBER 1995 – REVISED OCTOBER 1996  
DW PACKAGE  
(TOP VIEW)  
Provides System Clock Solution for  
Pentium /82430HX/82430VX and  
PentiumPro 82440FX Chipsets  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
REF0  
REF1  
CC  
X1  
Four Host-Clock Outputs With  
Programmable Frequency  
(50 MHz, 60 MHz, and 66 MHz)  
2
3
X2  
V
CC  
4
GND  
OE  
HCLK0  
HCLK1  
SBCLK  
FCCLK  
GND  
PCLK0  
PCLK1  
Six PCI Clock Outputs at Half-CPU  
Frequency  
5
6
One 48-MHz Universal Serial Bus (USB)  
Clock Output  
7
8
V
CC  
One 24-MHz Floppy Controller Output  
9
HCLK2  
HCLK3  
GND  
SEL1  
SEL0  
V
CC  
10  
11  
12  
13  
14  
PCLK2  
PCLK3  
GND  
PCLK4  
PCLK5  
Two 14.318-MHz Reference Clock Outputs  
All Output Clock Frequencies Derived From  
Single 14.31818-MHz Crystal Input  
LVTTL-Compatible Inputs and Outputs  
V
CC  
Internal Loop Filters for Phase-Lock Loops  
Eliminate the Need for External  
Components  
Operates at 3.3-V V  
CC  
Packaged in Plastic Small-Outline Package  
description  
The CDC9843 is a high-performance clock synthesizer/driver that generates the system clocks necessary to  
support Pentium /82430HX/82430VX and PentiumPro 82440FX chipsets. Four host-clock outputs (HCLKn)  
are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control  
inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to  
4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz  
(SBCLK), a floppy controller clock at 24 MHz (FCCLK), and two 14.318-MHz reference clock outputs (REF0,  
REF1) are provided.  
All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock input can be provided  
at the X1 input instead of a crystal input.  
Two phase-locked loops (PLLs) are used to generate the host clock frequency and the 48-MHz clock frequency.  
On-chip loop filters and internal feedback eliminate the need for external components. The PCI-clock frequency  
and floppy controller frequency are derived directly from the host-clock frequency and USB frequency,  
respectively. The PLL circuit can be bypassed in the test mode (i.e., SEL0 = SEL1 = H) to distribute a test clock  
provided at the X1 input.  
Thehost-andPCI-clockoutputsprovidelow-skew/low-jitterclocksignalsforreliableclockoperation. Alloutputs  
are 3 state and are enabled via OE.  
BecausetheCDC9843isbasedonPLLcircuitry, itrequiresastabilizationtimetoachievephase-lockofthePLL.  
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal  
at the X1, as well as following any changes to the OE or SELn inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Pentium is a trademark of Intel Corporation.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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