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CDC9841DW PDF预览

CDC9841DW

更新时间： 2024-11-19 04:11:43
品牌 Logo 应用领域
德州仪器 - TI 晶体驱动器时钟发生器微控制器和处理器外围集成电路光电二极管输出元件PC
页数 文件大小 规格书
9页 135K
描述
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

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中文翻译

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CDC9841DW 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, SOIC-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.8Is Samacsys：N
JESD-30 代码：R-PDSO-G28长度：17.9 mm
端子数量：28最高工作温度：70 °C
最低工作温度：最大输出时钟频率：66 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP28,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：14.31818 MHz
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Clock Generators最大压摆率：50 mA
最大供电电压：3.6 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CDC9841DW 数据手册

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CDC9841  
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS458D – DECEMBER 1994 – REVISED APRIL 1996  
DW PACKAGE  
(TOP VIEW)  
Four CPU Clock Outputs With  
Programmable Frequency  
(50 MHz, 60 MHz, and 66 MHz)  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
REF0  
REF1  
CC  
X1  
Six Clock Outputs at Half-CPU Frequency  
for PCI  
2
3
X2  
V
CC  
One 24-MHz Clock Output  
4
GND  
OE  
PCLK0  
PCLK1  
CLK12  
CLK24  
GND  
BCLK2  
BCLK3  
5
One 12-MHz Clock Output  
6
Two 14.318-MHz Reference Outputs  
7
All Output Clock Frequencies Derived From  
a Single 14.31818-MHz Crystal Input  
8
V
CC  
9
PCLK2  
PCLK3  
GND  
SEL1  
SEL0  
V
CC  
LVTTL-Compatible Inputs and Outputs  
10  
11  
12  
13  
14  
BCLK4  
BCLK5  
GND  
BCLK1  
BCLK0  
Internal Loop Filters for Phase-Lock Loops  
Eliminate the Need for External  
Components  
Operates at 3.3 V  
CC  
V
CC  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
Packaged in Plastic Small-Outline Package  
description  
The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals  
necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs  
(PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1  
control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency  
ofPCLKnandaredelayed1nsto4nsfromtherisingedgeoftheCPUclock. Inaddition, thefourfixed-frequency  
outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz  
input reference (REF0, REF1).  
The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be  
provided at X1 instead of a crystal input.  
Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop  
filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock  
frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can  
be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.  
Becausethe CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.  
This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal  
at the X1 input, as well as following any changes to the SELn inputs.  
PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state  
and are enabled via OE.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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CDC9841DW 替代型号

型号 品牌 替代类型 描述 数据表
CY2272PVC-1 CYPRESS

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