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CDC925DL

更新时间： 2024-11-16 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 晶体驱动器时钟发生器微控制器和处理器外围集成电路光电二极管输出元件PC
页数 文件大小 规格书
18页 255K
描述
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

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中文翻译

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CDC925DL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
其他特性：ALSO REQUIRES 3.3V SUPPLYJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
湿度敏感等级：2端子数量：56
最高工作温度：85 °C最低工作温度：
最大输出时钟频率：133 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5,3.3 V
主时钟/晶体标称频率：14.318 MHz认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Clock Generators
最大压摆率：146 mA最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CDC925DL 数据手册

 浏览型号CDC925DL的Datasheet PDF文件第2页浏览型号CDC925DL的Datasheet PDF文件第3页浏览型号CDC925DL的Datasheet PDF文件第4页浏览型号CDC925DL的Datasheet PDF文件第5页浏览型号CDC925DL的Datasheet PDF文件第6页浏览型号CDC925DL的Datasheet PDF文件第7页 
CDC925  
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS  
WITH 3-STATE OUTPUTS  
SCAS633 – JULY 28, 1999  
DL PACKAGE  
(TOP VIEW)  
Supports Pentium III Class Motherboards  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
REF0  
REF1  
V
2.5V  
DD  
Includes Spread Spectrum Clocking (SSC),  
0.34% Downspread for Reduced EMI  
Performance  
2
APIC2  
APIC1  
APIC0  
GND  
3
4
V
V
V
3.3V  
XIN  
DD  
Power Management Control Terminals  
5
6
XOUT  
GND  
V
2.5V  
Low Output Skew and Jitter for Clock  
Distribution  
DD  
7
CPU_DIV2(1)  
CPU_DIV2(0)  
GND  
8
PCI_F  
PCI1  
2.5-V and 3.3-V Supplies  
9
Generates the Following Clocks:  
– 4 CPU (2.5 V, 100/133 MHz)  
– 7 PCI (3.3 V, 33.3 MHz)  
– 1 PCI_F (Free Running, 3.3 V, 33.3 MHz)  
– 2 CPU/2 (2.5 V, 50/66 MHz)  
– 3 APIC (2.5 V, 16.67 MHz)  
– 4 3V66 (3.3 V, 66 MHz)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
3.3V  
V
2.5V  
DD  
DD  
PCI2  
PCI3  
GND  
PCI4  
PCI5  
3.3V  
CPU3  
CPU2  
GND  
V
2.5V  
DD  
CPU1  
CPU0  
GND  
– 2 REF (3.3 V, 14.318 MHz)  
– 1 48MHz (3.3 V, 48 MHz)  
DD  
PCI6  
PCI7  
GND  
GND  
V
3.3V  
DD  
Packaged in 56-Pin SSOP Package  
GND  
Designed for Use with TI’s Direct Rambus  
Clock Generators (CDCR81, CDCR82,  
CDCR83)  
PCI_STOP  
CPU_STOP  
PWR_DWN  
SPREAD  
SEL1  
3V66(0)  
3V66(1)  
V
3.3V  
DD  
description  
GND  
The CDC925 is a clock synthesizer/driver that  
generates system clocks necessary to support  
Intel Pentium III systems on CPU, CPU_DIV2,  
3V66, PCI, APIC, 48MHz, and REF clock signals.  
3V66(2)  
3V66(3)  
SEL0  
V
3.3V  
DD  
V
3.3V  
48MHz  
GND  
DD  
SEL133/100  
All output frequencies are generated from a  
14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two  
phase-lockedloops(PLLs)areused, onetogeneratethehostfrequenciesandtheothertogeneratethe48-MHz  
clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.  
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All  
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.  
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN  
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down  
completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or  
CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals,  
the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.  
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding  
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Intel and Pentium III are trademarks of Intel Corporation.  
Direct Rambus and Rambus are trademarks of Rambus Inc.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

中文翻译

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