5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 时钟发生器> CDC930DLR
CDC930DLR PDF预览

CDC930DLR

更新时间： 2024-11-17 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件PC时钟
页数 文件大小 规格书
17页 362K
描述
133MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, PLASTIC, SSOP-56

阅读下载

中文翻译

获取价格

CDC930DLR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.74
JESD-30 代码：R-PDSO-G56长度：18.415 mm
端子数量：56最高工作温度：85 °C
最低工作温度：最大输出时钟频率：133 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Clock Generators最大压摆率：250 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.49 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CDC930DLR 数据手册

 浏览型号CDC930DLR的Datasheet PDF文件第2页浏览型号CDC930DLR的Datasheet PDF文件第3页浏览型号CDC930DLR的Datasheet PDF文件第4页浏览型号CDC930DLR的Datasheet PDF文件第5页浏览型号CDC930DLR的Datasheet PDF文件第6页浏览型号CDC930DLR的Datasheet PDF文件第7页 
SCAS641 – JULY 2000  
DL PACKAGE  
(TOP VIEW)  
Generates Clocks for Pentium 4  
Microprocessors  
Uses a 14.318 MHz Crystal Input to  
Generate Multiple Output Frequencies  
GND  
REF0/MultSel0  
REF1/MultSel1  
V
3.3V  
DD  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
3VMREF  
3VMREF  
GND  
2
Includes Spread Spectrum Clocking (SSC),  
0.6% Downspread for Reduced EMI With  
3
V
V
V
V
3.3V  
XIN  
4
DD  
†
Theoretical EMI Damping of 7 dB  
SPREAD  
HCLK(1)  
HCLK(1)  
5
Power Management Control Terminals  
XOUT  
GND  
PCI0  
PCI1  
3.3V  
6
7
Low Output Skew and Jitter for Clock  
Distribution  
V
3.3V  
8
DD  
HCLK(2)  
HCLK(2)  
GND  
9
Operates From Single 3.3-V Supply  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DD  
Consumes Less Than 30-mA Power-Down  
Current  
PCI2  
PCI3  
GND  
PCI4  
PCI5  
45 HCLK(3)  
Generates the Following Clocks:  
– 4 HCLK (Host) (Different Pairs–  
100/133 MHz)  
– 1 3VMREF Pair (3.3 V, 180 Shifted  
50/66 MHz)  
– 10 PCI (3.3 V, 33.3 MHz)  
– 2 REF (3.3 V, 14.318 MHz)  
– 4 3V66 MHz (3.3 V, 66 MHz)  
– 2 3V48 MHz (3.3 V, 48 MHz)  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
HCLK(3)  
3.3V  
V
DD  
HCLK(4)  
HCLK(4)  
GND  
3.3V  
DD  
PCI6  
PCI7  
GND  
PCI8  
PCI9  
I_REF  
V
3.3V  
DD  
GND  
3.3V  
V
DD  
Packaged in 56-Pin SSOP Package  
3.3V  
3V66(0)  
3V66(1)  
GND  
DD  
SEL100/133  
GND  
description  
3V48(0)/SelA  
3V48(1)/SelB  
GND  
The CDC930 is a differential clock synthesizer/  
driver that generates HCLK/HCLK, 3VMREF/  
3VMREF, PCI, 3V66, 3V48, REF system clock  
signals to support a computer system with a  
3V66(2)  
3V66(3)  
V
3.3V  
DD  
PWRDWN  
V
3.3V  
DD  
Pentium 4 microprocessor and  
Rambus memory subsystem.  
a
Direct  
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided  
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies  
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external  
components. Thehost, PCI clock and 48-MHzclockoutputsprovidelow-skew/low-jitter clock signalsfor reliable  
clock operation. All outputs have 3-state capability, which can be selected using control inputs SEL133, SelA  
and SelB.  
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to  
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down  
mode in which HCLK is driven at 2 I  
, HCLK is not driven, and all others are set low.  
REF  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
This is system design dependant.  
Intel and Pentium 4 are trademarks of Intel Corporation.  
Rambus is a trademark of Rambus Corporation.  
Copyright 2000, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
1234567...17

中文翻译

下载PDF

与CDC930DLR相关器件

型号 品牌 获取价格 描述 数据表
CDC950 TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGG TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGG4 TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGR TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGRG4 TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC960 TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC960DL TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC960DLG4 TI

获取价格

 		200-MHz Clock Synthesizer/Driver with Spread Spectrum & Device Control Interface 4
CDC960DLR TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC9841 TI

获取价格

 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

与CDC930DLR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证