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CDC950DGGRG4 PDF预览

CDC950DGGRG4

更新时间： 2024-11-18 23:14:31
品牌 Logo 应用领域
德州仪器 - TI 驱动器PC时钟
页数 文件大小 规格书
16页 259K
描述
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

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中文翻译

获取价格

CDC950DGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.77JESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
湿度敏感等级：2端子数量：48
最高工作温度：85 °C最低工作温度：
最大输出时钟频率：133 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：14.8 MHz认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大压摆率：200 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CDC950DGGRG4 数据手册

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SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003  
DGG PACKAGE  
(TOP VIEW)  
D
D
D
Generates Clocks for Next Generation  
Microprocessors  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
CLK33  
3.3V  
SEL100/133  
GND  
1
48  
47  
46  
45  
44  
43  
V
2
DD  
Includes Spread Spectrum Clocking (SSC),  
0.6% Downspread for Reduced EMI With  
Theoretical EMI of 7 dB  
3V48/SelA  
3V48/SelB  
GND  
AV 3.3V  
3
DD  
AGND  
4
PWRDWN  
5
D
D
Power Management Control Terminals  
V
3.3V  
V
3.3V  
6
DD  
DD  
HCLK(0)  
HCLK(0)  
GND  
7
42 HCLK(4)  
41 HCLK(4)  
40 GND  
Low Output Skew and Jitter for Clock  
Distribution  
8
9
D
Operates From a Single 3.3-V Supply  
10  
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39  
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28  
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HCLK(1)  
HCLK(1)  
HCLK(5)  
HCLK(5)  
D
Generates the Following Clocks:  
− 8 Host (Diff Pairs, 100/133 MHz)  
− 1 CLK33 (3.3 V, 33.3 MHz)  
− 1 REFCLK (3.3 V, 14.318 MHz)  
− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)  
V
3.3V  
V
3.3V  
DD  
DD  
HCLK(2)  
HCLK(2)  
GND  
HCLK(6)  
HCLK(6)  
GND  
D
Packaged in a 48-Pin TSSOP Package  
HCLK(3)  
HCLK(3)  
HCLK(7)  
HCLK(7)  
description  
V
3.3V  
V
3.3V  
DD  
DD  
REFCLK  
SPREAD  
GND  
MultSel0  
MultSel1  
GND  
The CDC950 is a differential clock synthesizer/  
driver that generates HCLK/HCLK, CLK33, 3V48,  
and REFCLK system clock signals to support a  
computer system with next generation processors  
and double data rate (DDR) memory subsystems.  
XIN  
AGND  
I_REF  
XOUT  
V
3.3V  
AV 3.3V  
DD  
DD  
All output frequencies are generated from a  
14.318-MHz crystal input. A reference clock input  
can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the  
host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the  
need for external components.  
The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock  
operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,  
3V48/SelA, and 3V48/SelB.  
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the  
PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers  
down completely with the HOST clock at 2 × I  
, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are  
in a low-level output state and 3V48B is in a high-level output state.  
REF  
The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding  
setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.  
Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up, as well as following changes to the SEL inputs. With the  
use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time  
starts. The CDC950 is characterized for operation from 0°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2001 − 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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CDC950DGGRG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC950DGGR TI

完全替代

 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGG4 TI

类似代替

 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGG TI

类似代替

 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

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