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CDC960

更新时间： 2024-11-29 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 驱动器时钟
页数 文件大小 规格书
38页 551K
描述
200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE

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中文翻译

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CDC960 数据手册

 浏览型号CDC960的Datasheet PDF文件第2页浏览型号CDC960的Datasheet PDF文件第3页浏览型号CDC960的Datasheet PDF文件第4页浏览型号CDC960的Datasheet PDF文件第5页浏览型号CDC960的Datasheet PDF文件第6页浏览型号CDC960的Datasheet PDF文件第7页 
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SCAS675 – APRIL 2002  
DL PACKAGE  
(TOP VIEW)  
D
D
D
Generates Clocks for AMD-K8 Clawhammer  
Desktop Systems  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
FS0 & REF0  
FS1 & REF1  
GND  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
2
3
4
5
6
7
8
9
DD  
Includes Spread Spectrum Clocking (SSC),  
0.5% Downspread for Reduced EMI  
XIN  
XOUT  
GND  
V
DD  
FS2 & REF2  
SPREAD  
D
Power Management Control Terminals  
D
SMBus Serial Interface Provides Output  
Enable and Control  
PCI/LDT_SEL  
PCI/LDT0  
V
DDA  
GNDA  
CPU0  
CPU0  
GND  
PCI/LDT1  
D
Low-Output Skew and Low Jitter for Clock  
Distribution  
V
DD  
GND  
PCI/LDT2  
LDT_Stop  
PCI0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
Operates From Single 3.3-V Supply  
V
DD  
D
Generates the Following Clocks:  
– 2 CPU (3.3 V, 180° shifted pairs,  
200/166/133/100 MHz)  
CPU1  
CPU1  
PCI1  
V
DD  
– 6 PCI (3.3 V, 33 MHz)  
GND  
GND  
– 1 PCI_F (3.3 V, 33 MHz)  
– 3 REF (3.3 V, 14.318 MHz)  
– 1 USB (3.3 V, 48 MHz)  
V
GNDF  
DD  
PCI2  
PCI3  
V
DDF  
USB  
GND  
– 1 FDC (3.3 V, 24 MHz or 48 MHz)  
V
†
DD  
– 3 PCI/LDT (3.3 V, 33 MHz or 66 MHz)  
GND  
PCI4  
V
DD  
D
Packaged in 48-Pin SSOP Package  
24/48_SEL & FDC  
GND  
PCI5  
description  
PCI_F  
SDATA  
The CDC960 is a clock synthesizer/driver and  
PCI_Stop  
SCLK  
buffer that generates CPU, PCI, PCI/LDT, USB,  
FDC, and REF system clock signals to support  
PCs with an AMD-K8 Clawhammer-class system.  
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided  
at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this  
case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.  
On-chip loop filters and internal feedback eliminate the need for external components.  
The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The  
implementation is as a slave with read and write capability. The device address is specified in the SMBus serial  
interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors  
(typically 150 kΩ).  
Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs  
default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level  
control bit is written to the control register. The registers must be accessed in sequential order (i.e., random  
access of the registers not supported).  
The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter  
clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control  
inputs FS0, FS1, and FS2 at power-up preset condition.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
LDT is equivalent to HT66 shown on AMD specification.  
Copyright 2002, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...38

中文翻译

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