5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 时钟发生器> CDC950
CDC950 PDF预览

CDC950

更新时间： 2024-11-18 23:14:31
品牌 Logo 应用领域
德州仪器 - TI 驱动器PC时钟
页数 文件大小 规格书
16页 259K
描述
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

阅读下载

中文翻译

获取价格

CDC950 数据手册

 浏览型号CDC950的Datasheet PDF文件第2页浏览型号CDC950的Datasheet PDF文件第3页浏览型号CDC950的Datasheet PDF文件第4页浏览型号CDC950的Datasheet PDF文件第5页浏览型号CDC950的Datasheet PDF文件第6页浏览型号CDC950的Datasheet PDF文件第7页 
ꢀ ꢁꢀ ꢂꢃ ꢄ  
ꢅ ꢆ ꢆ ꢇꢈꢉ ꢊ ꢁꢋ ꢌꢌ ꢍꢎ ꢍꢏꢐ ꢋꢑ ꢒ ꢀꢒ ꢓ ꢀꢔ ꢕꢖ ꢏꢐ ꢉꢍꢕꢋ ꢗ ꢍꢎꢘ ꢁꢎꢋ ꢙ ꢍ ꢎ ꢌꢓ ꢎ  
ꢚꢀ ꢈ ꢓꢐ ꢉꢍ ꢎꢛꢓ ꢑꢎꢁꢕ ꢘꢕ ꢍ ꢎꢙ ꢍꢎ ꢕ  
SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003  
DGG PACKAGE  
(TOP VIEW)  
D
D
D
Generates Clocks for Next Generation  
Microprocessors  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
CLK33  
3.3V  
SEL100/133  
GND  
1
48  
47  
46  
45  
44  
43  
V
2
DD  
Includes Spread Spectrum Clocking (SSC),  
0.6% Downspread for Reduced EMI With  
Theoretical EMI of 7 dB  
3V48/SelA  
3V48/SelB  
GND  
AV 3.3V  
3
DD  
AGND  
4
PWRDWN  
5
D
D
Power Management Control Terminals  
V
3.3V  
V
3.3V  
6
DD  
DD  
HCLK(0)  
HCLK(0)  
GND  
7
42 HCLK(4)  
41 HCLK(4)  
40 GND  
Low Output Skew and Jitter for Clock  
Distribution  
8
9
D
Operates From a Single 3.3-V Supply  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
HCLK(1)  
HCLK(1)  
HCLK(5)  
HCLK(5)  
D
Generates the Following Clocks:  
− 8 Host (Diff Pairs, 100/133 MHz)  
− 1 CLK33 (3.3 V, 33.3 MHz)  
− 1 REFCLK (3.3 V, 14.318 MHz)  
− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)  
V
3.3V  
V
3.3V  
DD  
DD  
HCLK(2)  
HCLK(2)  
GND  
HCLK(6)  
HCLK(6)  
GND  
D
Packaged in a 48-Pin TSSOP Package  
HCLK(3)  
HCLK(3)  
HCLK(7)  
HCLK(7)  
description  
V
3.3V  
V
3.3V  
DD  
DD  
REFCLK  
SPREAD  
GND  
MultSel0  
MultSel1  
GND  
The CDC950 is a differential clock synthesizer/  
driver that generates HCLK/HCLK, CLK33, 3V48,  
and REFCLK system clock signals to support a  
computer system with next generation processors  
and double data rate (DDR) memory subsystems.  
XIN  
AGND  
I_REF  
XOUT  
V
3.3V  
AV 3.3V  
DD  
DD  
All output frequencies are generated from a  
14.318-MHz crystal input. A reference clock input  
can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the  
host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the  
need for external components.  
The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock  
operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,  
3V48/SelA, and 3V48/SelB.  
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the  
PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers  
down completely with the HOST clock at 2 × I  
, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are  
in a low-level output state and 3V48B is in a high-level output state.  
REF  
The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding  
setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.  
Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up, as well as following changes to the SEL inputs. With the  
use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time  
starts. The CDC950 is characterized for operation from 0°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢚ
ꢚ
ꢎ
ꢓ
ꢬ
ꢁ
ꢧ
ꢜ
ꢀ
ꢥ
ꢐ
ꢦ
ꢋ
ꢠ
ꢓ
ꢞ
ꢏ
ꢟ
ꢁ
ꢑ
ꢐ
ꢑ
ꢝ
ꢞ
ꢨ
ꢟ
ꢠ
ꢦ
ꢡ
ꢢ
ꢣ
ꢣ
ꢤ
ꢤ
ꢝ
ꢝ
ꢠ
ꢠ
ꢞ
ꢞ
ꢝ
ꢥ
ꢥ
ꢩ
ꢦ
ꢧ
ꢡ
ꢡ
ꢨ
ꢨ
ꢞ
ꢤ
ꢣ
ꢢ
ꢥ
ꢥ
ꢠ
ꢟ
ꢩ
ꢐꢨ  
ꢧ
ꢪ
ꢥ
ꢫ
ꢝ
ꢦ
ꢣ
ꢥ
ꢤ
ꢝ
ꢤ
ꢠ
ꢡ
ꢞ
ꢧ
ꢬ
ꢣ
ꢞ
ꢤ
ꢤ
ꢨ
ꢥ
ꢭ
Copyright 2001 − 2003, Texas Instruments Incorporated  
ꢡ
ꢠ
ꢦ
ꢤ
ꢠ
ꢡ
ꢢ
ꢤ
ꢠ
ꢥ
ꢩ
ꢝ
ꢟ
ꢝ
ꢦ
ꢨ
ꢡ
ꢤ
ꢮ
ꢤ
ꢨ
ꢡ
ꢠ
ꢟ
ꢯ
ꢣ
ꢋ
ꢞ
ꢢ
ꢨ
ꢥ
ꢤ
ꢣ
ꢞ
ꢬ
ꢣ
ꢡ
ꢬ
ꢰ
ꢣ
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
ꢡ
ꢡ
ꢣ
ꢞ
ꢤ
ꢱ
ꢭ
ꢚ
ꢡ
ꢠ
ꢬ
ꢧ
ꢦ
ꢤ
ꢝ
ꢠ
ꢞ
ꢩ
ꢡ
ꢠ
ꢦ
ꢨ
ꢥ
ꢥ
ꢝ
ꢞ
ꢲ
ꢬ
ꢠ
ꢨ
ꢥ
ꢞ
ꢠ
ꢤ
ꢞ
ꢨ
ꢦ
ꢨ
ꢥ
ꢥ
ꢣ
ꢡ
ꢝ
ꢫ
ꢱ
ꢝ
ꢞ
ꢦ
ꢫ
ꢧ
ꢬ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

下载PDF

与CDC950相关器件

型号 品牌 获取价格 描述 数据表
CDC950DGG TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGG4 TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGR TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC950DGGRG4 TI

获取价格

 		133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS
CDC960 TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC960DL TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC960DLG4 TI

获取价格

 		200-MHz Clock Synthesizer/Driver with Spread Spectrum & Device Control Interface 4
CDC960DLR TI

获取价格

 		200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERF
CDC9841 TI

获取价格

 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS
CDC9841DW TI

获取价格

 		PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

与CDC950相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证