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CDC950

更新时间： 2024-09-27 23:14:31
品牌 Logo 应用领域
德州仪器 - TI 驱动器PC时钟
页数 文件大小 规格书
16页 259K
描述
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS

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CDC950 数据手册

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SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003  
DGG PACKAGE  
(TOP VIEW)  
D
D
D
Generates Clocks for Next Generation  
Microprocessors  
Uses a 14.318-MHz Crystal Input to  
Generate Multiple Output Frequencies  
CLK33  
3.3V  
SEL100/133  
GND  
1
48  
47  
46  
45  
44  
43  
V
2
DD  
Includes Spread Spectrum Clocking (SSC),  
0.6% Downspread for Reduced EMI With  
Theoretical EMI of 7 dB  
3V48/SelA  
3V48/SelB  
GND  
AV 3.3V  
3
DD  
AGND  
4
PWRDWN  
5
D
D
Power Management Control Terminals  
V
3.3V  
V
3.3V  
6
DD  
DD  
HCLK(0)  
HCLK(0)  
GND  
7
42 HCLK(4)  
41 HCLK(4)  
40 GND  
Low Output Skew and Jitter for Clock  
Distribution  
8
9
D
Operates From a Single 3.3-V Supply  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
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35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
HCLK(1)  
HCLK(1)  
HCLK(5)  
HCLK(5)  
D
Generates the Following Clocks:  
− 8 Host (Diff Pairs, 100/133 MHz)  
− 1 CLK33 (3.3 V, 33.3 MHz)  
− 1 REFCLK (3.3 V, 14.318 MHz)  
− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)  
V
3.3V  
V
3.3V  
DD  
DD  
HCLK(2)  
HCLK(2)  
GND  
HCLK(6)  
HCLK(6)  
GND  
D
Packaged in a 48-Pin TSSOP Package  
HCLK(3)  
HCLK(3)  
HCLK(7)  
HCLK(7)  
description  
V
3.3V  
V
3.3V  
DD  
DD  
REFCLK  
SPREAD  
GND  
MultSel0  
MultSel1  
GND  
The CDC950 is a differential clock synthesizer/  
driver that generates HCLK/HCLK, CLK33, 3V48,  
and REFCLK system clock signals to support a  
computer system with next generation processors  
and double data rate (DDR) memory subsystems.  
XIN  
AGND  
I_REF  
XOUT  
V
3.3V  
AV 3.3V  
DD  
DD  
All output frequencies are generated from a  
14.318-MHz crystal input. A reference clock input  
can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the  
host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the  
need for external components.  
The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock  
operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,  
3V48/SelA, and 3V48/SelB.  
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. With a logic high-level on the  
PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers  
down completely with the HOST clock at 2 × I  
, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are  
in a low-level output state and 3V48B is in a high-level output state.  
REF  
The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding  
setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.  
Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up, as well as following changes to the SEL inputs. With the  
use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time  
starts. The CDC950 is characterized for operation from 0°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2001 − 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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