Datasheet > CDC857-3

CDC857-3

更新时间： 2024-11-19 22:23:59

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
12页	159K
描述
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

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CDC857-3 数据手册

CDC857-2, CDC857-3

2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

DGG PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Distribution for

Double Data Rate Synchronous DRAM

Applications

GND

Distributes One Differential Clock Input to

Ten Differential Outputs

External Feedback Pins (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Clock Input

Operates at V

= 2.5 V and AV

= 3.3 V

GND

Packaged in Plastic 48-Pin (DGG) Thin

Shrink Small-Outline Package (TSSOP)

Spread Spectrum Clocking Tracking

Capability to Reduce EMI

CLK

description

FBIN

The CDC857-2 and CDC857-3 are high-perfor-

mance, low-skew, low-jitter, phase-lock loop

(PLL) clock driver. They use a PLL to precisely

align, in both frequency and phase, the feedback

(FBOUT) output to the clock (CLK) input signal.

The CDC857-3 operates at 3.3 V (PLL) and 2.5 V

(output buffer). The CDC857-2 operates at

2.5 V (PLL and output buffer).

AGND

GND

FBOUT

GND

One bank of ten inverting and noninverting

outputs provide ten low-skew, low-jitter copies of

CLK. Output signal duty cycles are adjusted to

50%, independent of the duty cycle at CLK.

GND

All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs

switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance

state (3-state).

Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

feedback signals. The PLL can be bypassed for test purposes by strapping AV

to ground. If AV

is at GND

and V = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being

disabled, after AV

ramps up to its specified V

value, with G being kept low. The CDC857 is characterized

for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

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与CDC857-3相关器件

型号	品牌	获取价格	描述	数据表
CDC857-3DGG	ROCHESTER	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC857-3DGG	TI	获取价格	2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDC857-3DGGG4	TI	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC857-3DGGR	ROCHESTER	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
CDC906	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PW	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PWG4	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PWR	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906PWRG4	TI	获取价格	PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC90D48	SUMIDA	获取价格	Ferrite drum core construction

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