CDCVF2510PWLE

更新时间： 2024-10-02 13:06:43

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
11页	146K
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CDCVF2510PWLE 数据手册

CDCVF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS638 – DECEMBER 1999

PW PACKAGE

(TOP VIEW)

Designed to Meet and Exceed PC133

SDRAM Registered DIMM Specification

Rev. 1.1

AGND

CLK

Spread Spectrum Clock Compatible

Operating Frequency 50 MHz to 175 MHz

1Y0

1Y1

1Y2

GND

1Y3

Static Phase Error Distribution at 66MHz to

166 MHz is ±125 ps

1Y9

1Y8

GND

1Y7

1Y6

Jitter (cyc – cyc) at 66 MHz to 166 MHz Is

|70| ps

Advanced Deep Sub-Micron Process

Results in More Than 40% Lower Power

Consumption Versus Current Generation

PC133 Devices

1Y4

15 1Y5

FBOUT

FBIN

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Ten Outputs

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

25-Ω On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at 3.3 V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When

the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs

are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDCVF2510 is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与CDCVF2510PWLE相关器件

型号	品牌	获取价格	描述	数据表
CDCVF2510PWR	TI	获取价格	适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 \| PW \|
CDCVF2510PWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85
CDCVF310	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310_15	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PW	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWG4	TI	获取价格	High Performance 1:10 Clock Buffer for General Purpose Applications 24-TSSOP -40 to 85
CDCVF310PWR	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWRG4	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF855	TI	获取价格	2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
CDCVF855PW	TI	获取价格	2.5V Phase Lock Loop DDR Clock Driver 28-TSSOP -40 to 85

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