5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> CDCVF2510PWLE
CDCVF2510PWLE PDF预览

CDCVF2510PWLE

更新时间： 2024-11-20 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
11页 146K
描述
暂无描述

阅读下载

中文翻译

获取价格

CDCVF2510PWLE 数据手册

 浏览型号CDCVF2510PWLE的Datasheet PDF文件第2页浏览型号CDCVF2510PWLE的Datasheet PDF文件第3页浏览型号CDCVF2510PWLE的Datasheet PDF文件第4页浏览型号CDCVF2510PWLE的Datasheet PDF文件第5页浏览型号CDCVF2510PWLE的Datasheet PDF文件第6页浏览型号CDCVF2510PWLE的Datasheet PDF文件第7页 
CDCVF2510  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS638 – DECEMBER 1999  
PW PACKAGE  
(TOP VIEW)  
Designed to Meet and Exceed PC133  
SDRAM Registered DIMM Specification  
Rev. 1.1  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
Spread Spectrum Clock Compatible  
V
2
CC  
CC  
Operating Frequency 50 MHz to 175 MHz  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Static Phase Error Distribution at 66MHz to  
166 MHz is ±125 ps  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
5
6
Jitter (cyc – cyc) at 66 MHz to 166 MHz Is  
|70| ps  
7
8
Advanced Deep Sub-Micron Process  
Results in More Than 40% Lower Power  
Consumption Versus Current Generation  
PC133 Devices  
1Y4  
9
V
10  
11  
12  
15 1Y5  
CC  
G
V
14  
13  
CC  
FBOUT  
FBIN  
Available in Plastic 24-Pin TSSOP  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
Distributes One Clock Input to One Bank of  
Ten Outputs  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
25-Ω On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at 3.3 V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When  
the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs  
are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDCVF2510 is characterized for operation from 0°C to 85°C.  
For application information refer to application reports High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread  
Spectrum Clocking (SSC) (literature number SCAA039).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

下载PDF

与CDCVF2510PWLE相关器件

型号 品牌 获取价格 描述 数据表
CDCVF2510PWR TI

获取价格

 		适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 | PW |
CDCVF2510PWRG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85
CDCVF310 TI

获取价格

 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310_15 TI

获取价格

 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PW TI

获取价格

 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWG4 TI

获取价格

 		High Performance 1:10 Clock Buffer for General Purpose Applications 24-TSSOP -40 to 85
CDCVF310PWR TI

获取价格

 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWRG4 TI

获取价格

 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF855 TI

获取价格

 		2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
CDCVF855PW TI

获取价格

 		2.5V Phase Lock Loop DDR Clock Driver 28-TSSOP -40 to 85

与CDCVF2510PWLE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证