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CDCVF2510PWR PDF预览

CDCVF2510PWR

更新时间： 2024-11-21 11:07:55
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动动态存储器光电二极管逻辑集成电路时钟驱动器
页数 文件大小 规格书
11页 146K
描述
适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 | PW | 24 | 0 to 85

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中文翻译

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CDCVF2510PWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：5.19
Is Samacsys：N系列：2510
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
负载电容（CL）：25 pF逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：24实输出次数：10
最高工作温度：85 °C最低工作温度：
输出特性：SERIES-RESISTOR封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：3.9 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.1 ns座面最大高度：1.2 mm
子类别：Clock Driver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：OTHER
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：175 MHzBase Number Matches：1

CDCVF2510PWR 数据手册

 浏览型号CDCVF2510PWR的Datasheet PDF文件第2页浏览型号CDCVF2510PWR的Datasheet PDF文件第3页浏览型号CDCVF2510PWR的Datasheet PDF文件第4页浏览型号CDCVF2510PWR的Datasheet PDF文件第5页浏览型号CDCVF2510PWR的Datasheet PDF文件第6页浏览型号CDCVF2510PWR的Datasheet PDF文件第7页 
CDCVF2510  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS638 – DECEMBER 1999  
PW PACKAGE  
(TOP VIEW)  
Designed to Meet and Exceed PC133  
SDRAM Registered DIMM Specification  
Rev. 1.1  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
Spread Spectrum Clock Compatible  
V
2
CC  
CC  
Operating Frequency 50 MHz to 175 MHz  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Static Phase Error Distribution at 66MHz to  
166 MHz is ±125 ps  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
5
6
Jitter (cyc – cyc) at 66 MHz to 166 MHz Is  
|70| ps  
7
8
Advanced Deep Sub-Micron Process  
Results in More Than 40% Lower Power  
Consumption Versus Current Generation  
PC133 Devices  
1Y4  
9
V
10  
11  
12  
15 1Y5  
CC  
G
V
14  
13  
CC  
FBOUT  
FBIN  
Available in Plastic 24-Pin TSSOP  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
Distributes One Clock Input to One Bank of  
Ten Outputs  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
25-Ω On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at 3.3 V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When  
the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs  
are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDCVF2510 is characterized for operation from 0°C to 85°C.  
For application information refer to application reports High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread  
Spectrum Clocking (SSC) (literature number SCAA039).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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CDCVF2510PWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2510APW TI

完全替代

 3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

与CDCVF2510PWR相关器件

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CDCVF2510PWRG4 TI

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 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85
CDCVF310 TI

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 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310_15 TI

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 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PW TI

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 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWG4 TI

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 		High Performance 1:10 Clock Buffer for General Purpose Applications 24-TSSOP -40 to 85
CDCVF310PWR TI

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 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PWRG4 TI

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 		2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF855 TI

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 		2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
CDCVF855PW TI

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 		2.5V Phase Lock Loop DDR Clock Driver 28-TSSOP -40 to 85
CDCVF855PWG4 TI

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 		2.5V 锁相环路 DDR 时钟驱动器 | PW | 28 | -40 to 85

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